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Searched refs:b1001 (Results 1 – 25 of 65) sorted by relevance

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/external/llvm/test/TableGen/
DBitsInit.td44 bits<8> F1 = { 0, 1, 0b1001, 0, 0b0 }; // ok
45 bits<7> F2 = { 0, 1, 0b1001, 0, 0b0 }; // LHS doesn't have enough bits
46 bits<9> F3 = { 0, 1, 0b1001, 0, 0b0 }; // RHS doesn't have enough bits
48 bits<8> G1 = { 0, { 1, 0b1001, 0 }, 0b0 }; // ok
49 bits<8> G2 = { 0, { 1, 0b1001 }, 0, 0b0 }; // ok
50 bits<8> G3 = { 0, 1, { 0b1001 }, 0, 0b0 }; // ok
/external/llvm-project/llvm/test/TableGen/
DBitsInit.td44 bits<8> F1 = { 0, 1, 0b1001, 0, 0b0 }; // ok
45 bits<7> F2 = { 0, 1, 0b1001, 0, 0b0 }; // LHS doesn't have enough bits
46 bits<9> F3 = { 0, 1, 0b1001, 0, 0b0 }; // RHS doesn't have enough bits
48 bits<8> G1 = { 0, { 1, 0b1001, 0 }, 0b0 }; // ok
49 bits<8> G2 = { 0, { 1, 0b1001 }, 0, 0b0 }; // ok
50 bits<8> G3 = { 0, 1, { 0b1001 }, 0, 0b0 }; // ok
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td47 def : AT<"S1E1RP", 0b01, 0b000, 0b0111, 0b1001, 0b000>;
48 def : AT<"S1E1WP", 0b01, 0b000, 0b0111, 0b1001, 0b001>;
317 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
318 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
375 def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>;
396 def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>;
434 def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>;
472 def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>;
488 def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>;
504 def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td67 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
68 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
559 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
560 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
627 def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>;
648 def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>;
708 def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>;
746 def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>;
762 def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>;
778 def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>;
[all …]
DAArch64SVEInstrInfo.td202 defm FSCALE_ZPmZ : sve_fp_2op_p_zds_fscale<0b1001, "fscale", int_aarch64_sve_fscale>;
321 defm ORN_PPzPP : sve_int_pred_log<0b1001, "orn", int_aarch64_sve_orn_z>;
351 defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
397 defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>;
415 defm LDNF1SH_S_IMM : sve_mem_cldnf_si<0b1001, "ldnf1sh", Z_s, ZPR32>;
433 defm LDFF1SH_S : sve_mem_cldff_ss<0b1001, "ldff1sh", Z_s, ZPR32, GPR64shifted16>;
515 …defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4, null_frag, …
532 …defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw", null_frag, nxv2i32>;
545 …defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", null_frag, ZP…
562 …defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", null_frag, nul…
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td72 def : AT<"S1E1RP", 0b000, 0b0111, 0b1001, 0b000>;
73 def : AT<"S1E1WP", 0b000, 0b0111, 0b1001, 0b001>;
564 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
565 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
632 def : ROSysReg<"TRCIDR1", 0b10, 0b001, 0b0000, 0b1001, 0b111>;
653 def : ROSysReg<"TRCPIDR1", 0b10, 0b001, 0b0111, 0b1001, 0b111>;
713 def : WOSysReg<"PMSWINC_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b100>;
751 def : RWSysReg<"DBGBVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b100>;
767 def : RWSysReg<"DBGBCR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b101>;
783 def : RWSysReg<"DBGWVR9_EL1", 0b10, 0b000, 0b0000, 0b1001, 0b110>;
[all …]
/external/llvm-project/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td732 def CMP8rr : I8rr<0b1001,
736 def CMP16rr : I16rr<0b1001,
741 def CMP8rc : I8rc<0b1001,
745 def CMP16rc : I16rc<0b1001,
750 def CMP8ri : I8ri<0b1001,
754 def CMP16ri : I16ri<0b1001,
759 def CMP8mc : I8mc<0b1001,
764 def CMP16mc : I16mc<0b1001,
770 def CMP8mi : I8mi<0b1001,
775 def CMP16mi : I16mi<0b1001,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td732 def CMP8rr : I8rr<0b1001,
736 def CMP16rr : I16rr<0b1001,
741 def CMP8rc : I8rc<0b1001,
745 def CMP16rc : I16rc<0b1001,
750 def CMP8ri : I8ri<0b1001,
754 def CMP16ri : I16ri<0b1001,
759 def CMP8mc : I8mc<0b1001,
764 def CMP16mc : I16mc<0b1001,
770 def CMP8mi : I8mi<0b1001,
775 def CMP16mi : I16mi<0b1001,
[all …]
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp136 b1001 = 0x9, enumerator
155 { true, true, true, b1001, b1001, b0110, false, NONE },
157 { true, true, true, b1001, b1001, b1111, true, FILL },
158 { false, true, true, b1001, b1001, b0110, true, FILL },
160 { true, true, true, b1001, b1001, b1111, true, COPY },
161 { false, true, true, b1001, b1001, b0110, true, COPY },
/external/llvm/lib/Target/AVR/
DAVRInstrFormats.td102 let Inst{15-12} = 0b1001;
227 let Inst{15-12} = 0b1001;
367 let Inst{15-12} = 0b1001;
413 let Inst{15-12} = 0b1001;
499 let Inst{31-28} = 0b1001;
518 let Inst{15-12} = 0b1001;
DAVRInstrInfo.td482 def INCRd : FRd<0b1001,
489 def DECRd : FRd<0b1001,
507 def MULRdRr : FRdRr<0b1001, 0b11,
670 def COMRd : FRd<0b1001,
688 def NEGRd : FRd<0b1001,
1465 def PUSHRr : FRd<0b1001,
1483 def POPRd : FRd<0b1001,
1548 def LSRRd : FRd<0b1001,
1560 def ASRRd : FRd<0b1001,
1587 def RORRd : FRd<0b1001,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrFormats.td103 let Inst{15-12} = 0b1001;
228 let Inst{15-12} = 0b1001;
368 let Inst{15-12} = 0b1001;
414 let Inst{15-12} = 0b1001;
500 let Inst{31-28} = 0b1001;
519 let Inst{15-12} = 0b1001;
DAVRInstrInfo.td524 def INCRd : FRd<0b1001,
531 def DECRd : FRd<0b1001,
549 def MULRdRr : FRdRr<0b1001, 0b11,
712 def COMRd : FRd<0b1001,
730 def NEGRd : FRd<0b1001,
1572 def PUSHRr : FRd<0b1001,
1590 def POPRd : FRd<0b1001,
1650 def LSRRd : FRd<0b1001,
1662 def ASRRd : FRd<0b1001,
1694 def RORRd : FRd<0b1001,
[all …]
/external/llvm-project/llvm/lib/Target/AVR/
DAVRInstrFormats.td103 let Inst{15-12} = 0b1001;
230 let Inst{15-12} = 0b1001;
384 let Inst{15-12} = 0b1001;
432 let Inst{15-12} = 0b1001;
518 let Inst{31-28} = 0b1001;
537 let Inst{15-12} = 0b1001;
DAVRInstrInfo.td530 def INCRd : FRd<0b1001,
537 def DECRd : FRd<0b1001,
555 def MULRdRr : FRdRr<0b1001, 0b11,
718 def COMRd : FRd<0b1001,
735 def NEGRd : FRd<0b1001,
1588 def PUSHRr : FRd<0b1001,
1606 def POPRd : FRd<0b1001,
1666 def LSRRd : FRd<0b1001,
1678 def ASRRd : FRd<0b1001,
1710 def RORRd : FRd<0b1001,
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td1153 def VMOVRH : AVConv2I<0b11100001, 0b1001,
1172 def VMOVHR : AVConv4I<0b11100000, 0b1001,
1286 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1325 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1423 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1463 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1487 def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1508 def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1553 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
1558 def VTOUHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1111, 0b1001, 0,
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td271 defm : int_cond_alias<"ne", 0b1001>;
288 defm : int_cond_alias<"nz", 0b1001>; // same as ne
303 defm : fp_cond_alias<"e", 0b1001>;
314 defm : fp_cond_alias<"z", 0b1001>; // same as e
326 defm : cp_cond_alias<"0", 0b1001>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td270 defm : int_cond_alias<"ne", 0b1001>;
287 defm : int_cond_alias<"nz", 0b1001>; // same as ne
302 defm : fp_cond_alias<"e", 0b1001>;
313 defm : fp_cond_alias<"z", 0b1001>; // same as e
325 defm : cp_cond_alias<"0", 0b1001>;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td270 defm : int_cond_alias<"ne", 0b1001>;
287 defm : int_cond_alias<"nz", 0b1001>; // same as ne
302 defm : fp_cond_alias<"e", 0b1001>;
313 defm : fp_cond_alias<"z", 0b1001>; // same as e
325 defm : cp_cond_alias<"0", 0b1001>;
/external/llvm-project/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h119 TETT = 0b1001,
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td1319 def VMOVRH : AVConv2I<0b11100001, 0b1001,
1341 def VMOVHR : AVConv4I<0b11100000, 0b1001,
1469 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1515 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1624 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1671 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1701 def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1726 def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1737 def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011,
1785 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td1250 def VMOVRH : AVConv2I<0b11100001, 0b1001,
1272 def VMOVHR : AVConv4I<0b11100000, 0b1001,
1391 def VSITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1437 def VUITOH : AVConv1IHs_Encode<0b11101, 0b11, 0b1000, 0b1001,
1542 def VTOSIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1589 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1619 def VTOSIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1101, 0b1001,
1644 def VTOUIRH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1655 def VJCVT : AVConv1IsD_Encode<0b11101, 0b11, 0b1001, 0b1011,
1700 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0,
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td316 class V6_vL32b_nt_cur_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b1001>;
335 class V6_vL32b_nt_cur_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b1001>;
494 class V6_vL32b_nt_cur_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b1001>;
513 class V6_vL32b_nt_cur_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b1001>;
828 class V6_vlutvvb_enc : Enc_COPROC_VX_4op_r<0b1001>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td528 def C_EBREAK : RVInst16CR<0b1001, 0b10, (outs), (ins), "c.ebreak", "">, Sched<[]>;
532 def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
536 def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rs1_wb),
639 def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rs1_wb),
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoC.td533 def C_EBREAK : RVInst16CR<0b1001, 0b10, (outs), (ins), "c.ebreak", "">, Sched<[]>;
537 def C_JALR : RVInst16CR<0b1001, 0b10, (outs), (ins GPRNoX0:$rs1),
541 def C_ADD : RVInst16CR<0b1001, 0b10, (outs GPRNoX0:$rs1_wb),
644 def C_ADD_HINT : RVInst16CR<0b1001, 0b10, (outs GPRX0:$rs1_wb),

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