/external/llvm/lib/Target/AArch64/ |
D | AArch64SystemOperands.td | 100 def : DC<"CIVAC", 0b01, 0b011, 0b0111, 0b1110, 0b001>; 101 def : DC<"CISW", 0b01, 0b000, 0b0111, 0b1110, 0b010>; 316 def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; 361 def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; 362 def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; 380 def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>; 387 def : ROSysReg<"TRCAUTHSTATUS", 0b10, 0b001, 0b0111, 0b1110, 0b110>; 401 def : ROSysReg<"TRCCIDR2", 0b10, 0b001, 0b0111, 0b1110, 0b111>; 477 def : RWSysReg<"DBGBVR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b100>; 493 def : RWSysReg<"DBGBCR14_EL1", 0b10, 0b000, 0b0000, 0b1110, 0b101>; [all …]
|
/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64SystemOperands.td | 125 def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>; 126 def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>; 138 def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>; 142 def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>; 147 def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>; 151 def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>; 563 def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; 617 def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; 618 def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; 637 def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>; [all …]
|
D | AArch64SVEInstrInfo.td | 654 defm NORS_PPzPP : sve_int_pred_log<0b1110, "nors", null_frag>; 696 defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>; 742 defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>; 760 defm LDNF1SB_H_IMM : sve_mem_cldnf_si<0b1110, "ldnf1sb", Z_h, ZPR16>; 778 defm LDFF1SB_H : sve_mem_cldff_ss<0b1110, "ldff1sb", Z_h, ZPR16, GPR64shifted8>; 858 …defm GLD1D : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d", uimm5s8, AArch64ld1_gather_imm_z, … 875 …defm GLD1D : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d", AArch64ld1_gather_z, nxv2i… 888 …defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", AArch64ld1_gather_scaled_z, … 905 …defm GLD1D : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d", AArch64ld1_gather_sxtw_z, A… 918 …defm GLD1D : sve_mem_64b_gld_sv_32_scaled<0b1110, "ld1d", AArch64ld1_gather_sxtw_scaled_z,… [all …]
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64SystemOperands.td | 120 def : DC<"CIVAC", 0b011, 0b0111, 0b1110, 0b001>; 121 def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>; 133 def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>; 137 def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>; 142 def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>; 146 def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>; 558 def : ROSysReg<"DBGAUTHSTATUS_EL1", 0b10, 0b000, 0b0111, 0b1110, 0b110>; 612 def : ROSysReg<"CNTPCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b001>; 613 def : ROSysReg<"CNTVCT_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b010>; 632 def : ROSysReg<"TRCIDR6", 0b10, 0b001, 0b0000, 0b1110, 0b111>; [all …]
|
D | AArch64SVEInstrInfo.td | 326 defm NORS_PPzPP : sve_int_pred_log<0b1110, "nors", null_frag>; 356 defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>; 402 defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>; 420 defm LDNF1SB_H_IMM : sve_mem_cldnf_si<0b1110, "ldnf1sb", Z_h, ZPR16>; 438 defm LDFF1SB_H : sve_mem_cldff_ss<0b1110, "ldff1sb", Z_h, ZPR16, GPR64shifted8>; 518 …defm GLD1D : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d", uimm5s8, AArch64ld1_gather_imm, … 535 …defm GLD1D : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d", AArch64ld1_gather, nxv2i64>; 548 …defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", AArch64ld1_gather_scaled, ZP… 565 …defm GLD1D : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d", AArch64ld1_gather_sxtw, AAr… 578 …defm GLD1D : sve_mem_64b_gld_sv_32_scaled<0b1110, "ld1d", AArch64ld1_gather_sxtw_scaled, A… [all …]
|
/external/llvm-project/llvm/lib/Target/ARM/Utils/ |
D | ARMBaseInfo.h | 111 TEE = 0b1110,
|
/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfoV3.td | 207 let IClass = 0b1110; 237 let IClass = 0b1110;
|
D | HexagonInstrInfo.td | 612 let Inst{27-24} = 0b1110; 1741 defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>; 1938 defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>; 2022 def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>; 2094 def L2_loadrd_pcr : T_load_pcr <"memd", DoubleRegs, 0b1110>; 2180 def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>; 2276 def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>; 2324 let IClass = 0b1110; 2410 let IClass = 0b1110; 2411 let Inst{27-24} = 0b1110; [all …]
|
D | HexagonInstrInfoV5.td | 161 let IClass = 0b1110; 227 let IClass = 0b1110; 705 let IClass = 0b1110; 738 let IClass = 0b1110;
|
D | HexagonIsetDx.td | 228 let Inst{12-9} = 0b1110; 674 let Inst{12-9} = 0b1110;
|
/external/llvm/lib/Target/Lanai/ |
D | LanaiInstrFormats.td | 334 let Opcode = 0b1110; 362 let Opcode = 0b1110; 397 let Opcode = 0b1110;
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
D | LanaiInstrFormats.td | 333 let Opcode = 0b1110; 361 let Opcode = 0b1110; 396 let Opcode = 0b1110;
|
/external/llvm-project/llvm/lib/Target/Lanai/ |
D | LanaiInstrFormats.td | 333 let Opcode = 0b1110; 361 let Opcode = 0b1110; 396 let Opcode = 0b1110;
|
/external/llvm/lib/Target/Sparc/ |
D | SparcInstrAliases.td | 281 defm : int_cond_alias<"pos", 0b1110>; 308 defm : fp_cond_alias<"ule", 0b1110>; 331 defm : cp_cond_alias<"013", 0b1110>;
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
D | SparcInstrAliases.td | 280 defm : int_cond_alias<"pos", 0b1110>; 307 defm : fp_cond_alias<"ule", 0b1110>; 330 defm : cp_cond_alias<"013", 0b1110>;
|
/external/llvm-project/llvm/lib/Target/Sparc/ |
D | SparcInstrAliases.td | 280 defm : int_cond_alias<"pos", 0b1110>; 307 defm : fp_cond_alias<"ule", 0b1110>; 330 defm : cp_cond_alias<"013", 0b1110>;
|
/external/llvm/lib/Target/ARM/ |
D | ARMInstrNEON.td | 1517 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), 1540 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), 4280 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8", 4282 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary, 4390 defm VQRDMLAHsl : N3VMulOpSL_HS<0b1110, IIC_VMACi16D, IIC_VMACi32D, 4714 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32, 4716 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32, 4718 def VCEQhd : N3VD<0,0,0b01,0b1110,0, IIC_VBIND, "vceq", "f16", v4i16, v4f16, 4721 def VCEQhq : N3VQ<0,0,0b01,0b1110,0, IIC_VBINQ, "vceq", "f16", v8i16, v8f16, 4734 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32, [all …]
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMInstrVFP.td | 1700 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0, 1712 def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1, 1726 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1744 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1762 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1772 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 2378 def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins), 2442 def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$Rt), 2737 defm VSTR_FPCXTNS : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">; 2755 defm VLDR_FPCXTNS : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">;
|
D | ARMInstrNEON.td | 1537 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), 1568 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), 4439 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8", 4441 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary, 4551 defm VQRDMLAHsl : N3VMulOpSL_HS<0b1110, IIC_VMACi16D, IIC_VMACi32D, 5093 def VCEQfd : N3VD_cmp<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32, 5095 def VCEQfq : N3VQ_cmp<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32, 5097 def VCEQhd : N3VD_cmp<0,0,0b01,0b1110,0, IIC_VBIND, "vceq", "f16", v4i16, v4f16, 5100 def VCEQhq : N3VQ_cmp<0,0,0b01,0b1110,0, IIC_VBINQ, "vceq", "f16", v8i16, v8f16, 5113 def VCGEfd : N3VD_cmp<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32, [all …]
|
/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMInstrVFP.td | 1785 def VTOSHH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 0, 1797 def VTOSLH : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1001, 1, 1811 def VTOSHS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 0, 1829 def VTOSLS : AVConv1XInsS_Encode<0b11101, 0b11, 0b1110, 0b1010, 1, 1847 def VTOSHD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 0, 1857 def VTOSLD : AVConv1XInsD_Encode<0b11101, 0b11, 0b1110, 0b1011, 1, 2474 def VMRS_FPCXTNS : MovFromVFP<0b1110 /* fpcxtns */, (outs GPR:$Rt), (ins), 2538 def VMSR_FPCXTNS : MovToVFP<0b1110 /* fpcxtns */, (outs), (ins GPR:$Rt), 2838 defm VSTR_FPCXTNS : vfp_vstrldr_sysreg<0b0,0b1110, "fpcxtns">; 2862 defm VLDR_FPCXTNS : vfp_vstrldr_sysreg<0b1,0b1110, "fpcxtns">;
|
D | ARMInstrNEON.td | 1519 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), 1550 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), 4370 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8", 4372 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary, 4482 defm VQRDMLAHsl : N3VMulOpSL_HS<0b1110, IIC_VMACi16D, IIC_VMACi32D, 5086 def VCEQfd : N3VD_cmp<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32, 5088 def VCEQfq : N3VQ_cmp<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32, 5090 def VCEQhd : N3VD_cmp<0,0,0b01,0b1110,0, IIC_VBIND, "vceq", "f16", v4i16, v4f16, 5093 def VCEQhq : N3VQ_cmp<0,0,0b01,0b1110,0, IIC_VBINQ, "vceq", "f16", v8i16, v8f16, 5106 def VCGEfd : N3VD_cmp<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32, [all …]
|
/external/llvm-project/llvm/lib/Target/Mips/ |
D | MipsMSAInstrFormats.td | 36 let Inst{22-19} = 0b1110;
|
/external/llvm/lib/Target/Mips/ |
D | MipsMSAInstrFormats.td | 36 let Inst{22-19} = 0b1110;
|
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | MipsMSAInstrFormats.td | 36 let Inst{22-19} = 0b1110;
|
/external/llvm-project/llvm/lib/Target/RISCV/ |
D | RISCVInstrFormatsV.td | 67 def LSWidth512 : RISCVWidth<0b1110>;
|