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Searched refs:backend_instruction (Results 1 – 18 of 18) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_cfg.h95 backend_instruction *start();
96 const backend_instruction *start() const;
97 backend_instruction *end();
98 const backend_instruction *end() const;
108 backend_instruction *first_non_control_flow_inst();
109 backend_instruction *last_non_control_flow_inst();
124 static inline struct backend_instruction *
127 return (struct backend_instruction *)exec_list_get_head(&block->instructions); in bblock_start()
130 static inline const struct backend_instruction *
133 return (const struct backend_instruction *)exec_list_get_head_const(&block->instructions); in bblock_start_const()
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Dbrw_dead_control_flow.cpp51 backend_instruction *const inst = block->start(); in dead_control_flow_eliminate()
52 backend_instruction *const prev_inst = prev_block->end(); in dead_control_flow_eliminate()
60 backend_instruction *const else_inst = prev_inst; in dead_control_flow_eliminate()
68 backend_instruction *const endif_inst = inst; in dead_control_flow_eliminate()
69 backend_instruction *const if_inst = prev_inst; in dead_control_flow_eliminate()
104 backend_instruction *const if_inst = prev_inst; in dead_control_flow_eliminate()
105 backend_instruction *const else_inst = inst; in dead_control_flow_eliminate()
Dbrw_shader.cpp847 backend_instruction::is_commutative() const in is_commutative()
870 backend_instruction::is_3src(const struct gen_device_info *devinfo) const in is_3src()
876 backend_instruction::is_tex() const in is_tex()
897 backend_instruction::is_math() const in is_math()
912 backend_instruction::is_control_flow() const in is_control_flow()
929 backend_instruction::can_do_source_mods() const in can_do_source_mods()
953 backend_instruction::can_do_saturate() const in can_do_saturate()
998 backend_instruction::can_do_cmod() const in can_do_cmod()
1044 backend_instruction::reads_accumulator_implicitly() const in reads_accumulator_implicitly()
1057 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const in writes_accumulator_implicitly()
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Dbrw_predicated_break.cpp68 backend_instruction *jump_inst = block->end(); in opt_predicated_break()
73 backend_instruction *if_inst = block->prev()->end(); in opt_predicated_break()
77 backend_instruction *endif_inst = block->next()->start(); in opt_predicated_break()
124 backend_instruction *while_inst = while_block->start(); in opt_predicated_break()
Dbrw_schedule_instructions.cpp65 schedule_node(backend_instruction *inst, instruction_scheduler *sched);
69 backend_instruction *inst;
616 virtual int issue_time(backend_instruction *inst) = 0;
618 virtual void count_reads_remaining(backend_instruction *inst) = 0;
620 virtual void update_register_pressure(backend_instruction *inst) = 0;
621 virtual int get_register_pressure_benefit(backend_instruction *inst) = 0;
689 int issue_time(backend_instruction *inst);
692 void count_reads_remaining(backend_instruction *inst);
694 void update_register_pressure(backend_instruction *inst);
695 int get_register_pressure_benefit(backend_instruction *inst);
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Dbrw_ir.h92 struct backend_instruction : public exec_node { struct
105 void insert_after(bblock_t *block, backend_instruction *inst);
106 void insert_before(bblock_t *block, backend_instruction *inst);
122 struct backend_instruction {
Dbrw_disasm_info.h34 struct backend_instruction;
80 struct backend_instruction *inst, unsigned offset);
Dbrw_shader.h81 virtual void dump_instruction(const backend_instruction *inst) const = 0;
82 virtual void dump_instruction(const backend_instruction *inst, FILE *file) const = 0;
Dbrw_cfg.cpp108 ends_block(const backend_instruction *inst) in ends_block()
121 starts_block(const backend_instruction *inst) in starts_block()
162 foreach_inst_in_block(backend_instruction, inst, this) { in dump()
191 foreach_in_list_safe(backend_instruction, inst, instructions) { in cfg_t()
Dbrw_vec4.h309 void dump_instruction(const backend_instruction *inst) const;
310 void dump_instruction(const backend_instruction *inst, FILE *file) const;
Dbrw_ir_performance.cpp1259 const backend_instruction *inst, in accum_reg_of_channel()
1274 const backend_instruction *be_inst) in issue_fs_inst()
1394 const backend_instruction *be_inst) in issue_vec4_instruction()
1505 const backend_instruction *), in calculate_performance() argument
1543 foreach_inst_in_block(backend_instruction, inst, block) { in calculate_performance()
Dbrw_disasm_info.c130 struct backend_instruction *inst, unsigned offset) in disasm_annotate()
Dbrw_fs.h334 void dump_instruction(const backend_instruction *inst) const;
335 void dump_instruction(const backend_instruction *inst, FILE *file) const;
Dbrw_fs_register_coalesce.cpp331 foreach_block_and_inst_safe (block, backend_instruction, inst, cfg) { in register_coalesce()
Dbrw_ir_vec4.h269 class vec4_instruction : public backend_instruction {
Dbrw_vec4.cpp247 if (!backend_instruction::can_do_source_mods()) in can_do_source_mods()
256 if (!backend_instruction::can_do_cmod()) in can_do_cmod()
1586 vec4_visitor::dump_instruction(const backend_instruction *be_inst) const in dump_instruction()
1592 vec4_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) const in dump_instruction()
Dbrw_ir_fs.h324 class fs_inst : public backend_instruction {
Dbrw_fs.cpp460 if (!backend_instruction::can_do_source_mods()) in can_do_source_mods()
469 if (!backend_instruction::can_do_cmod()) in can_do_cmod()
7185 foreach_block_and_inst(block, backend_instruction, inst, cfg) { in dump_instructions()
7194 foreach_in_list(backend_instruction, inst, &instructions) { in dump_instructions()
7206 fs_visitor::dump_instruction(const backend_instruction *be_inst) const in dump_instruction()
7212 fs_visitor::dump_instruction(const backend_instruction *be_inst, FILE *file) const in dump_instruction()