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Searched refs:bank (Results 1 – 25 of 208) sorted by relevance

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/external/speex/libspeexdsp/
Dfilterbank.c56 FilterBank *bank; in filterbank_new() local
66 bank = (FilterBank*)speex_alloc(sizeof(FilterBank)); in filterbank_new()
67 bank->nb_banks = banks; in filterbank_new()
68 bank->len = len; in filterbank_new()
69 bank->bank_left = (int*)speex_alloc(len*sizeof(int)); in filterbank_new()
70 bank->bank_right = (int*)speex_alloc(len*sizeof(int)); in filterbank_new()
71 bank->filter_left = (spx_word16_t*)speex_alloc(len*sizeof(spx_word16_t)); in filterbank_new()
72 bank->filter_right = (spx_word16_t*)speex_alloc(len*sizeof(spx_word16_t)); in filterbank_new()
75 bank->scaling = (float*)speex_alloc(banks*sizeof(float)); in filterbank_new()
99 bank->bank_left[i] = id1; in filterbank_new()
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Dfilterbank.h54 void filterbank_destroy(FilterBank *bank);
56 void filterbank_compute_bank32(FilterBank *bank, spx_word32_t *ps, spx_word32_t *mel);
58 void filterbank_compute_psd16(FilterBank *bank, spx_word16_t *mel, spx_word16_t *psd);
61 void filterbank_compute_bank(FilterBank *bank, float *psd, float *mel);
62 void filterbank_compute_psd(FilterBank *bank, float *mel, float *psd);
/external/arm-trusted-firmware/drivers/st/gpio/
Dstm32_gpio.c32 static int ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) in ckeck_gpio_bank() argument
35 uint32_t bank_offset = stm32_get_gpio_bank_offset(bank); in ckeck_gpio_bank()
98 uint32_t bank; in dt_set_gpio_config() local
108 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; in dt_set_gpio_config()
134 bank_node = ckeck_gpio_bank(fdt, bank, pinctrl_node); in dt_set_gpio_config()
146 assert((unsigned long)clk == stm32_get_gpio_bank_clock(bank)); in dt_set_gpio_config()
148 set_gpio(bank, pin, mode, speed, pull, alternate, status); in dt_set_gpio_config()
203 void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed, in set_gpio() argument
206 uintptr_t base = stm32_get_gpio_bank_base(bank); in set_gpio()
207 unsigned long clock = stm32_get_gpio_bank_clock(bank); in set_gpio()
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/external/llvm-project/llvm/docs/GlobalISel/
DRegBankSelect.rst9 It iteratively maps instructions to a set of per-operand bank assignment.
29 * **Banks**: ``addRegBankCoverage`` --- which register bank covers each
32 * **Cross-Bank Copies**: ``copyCost`` --- the cost of a ``COPY`` from one bank
35 * **Default Mapping**: ``getInstrMapping`` --- the default bank assignments for
39 possible bank assignments for a given instruction.
43 mostly using existing information augmented by bank descriptions.
57 * **Fast** --- For each instruction, pick a target-provided "default" bank
61 target-provided bank assignment alternatives.
66 bank assignments.
72 bank, introducing cross-bank copies on most floating point operations.
/external/igt-gpu-tools/tools/
Dintel_l3_parity.c116 static int disable_rbs(int row, int bank, int sbank, int slice) in disable_rbs() argument
118 struct l3_log_register *reg = &l3logs[slice][bank][sbank]; in disable_rbs()
141 static void enables_rbs(int row, int bank, int sbank, int slice) in enables_rbs() argument
143 struct l3_log_register *reg = &l3logs[slice][bank][sbank]; in enables_rbs()
180 int row = 0, bank = 0, sbank = 0; in main() local
268 bank = atoi(optarg); in main()
269 if (bank >= num_banks() || bank >= MAX_BANKS_PER_SLICE) in main()
290 ret = sscanf(optarg, "%d,%d,%d", &row, &bank, &sbank); in main()
353 enables_rbs(row, bank, sbank, i); in main()
356 assert(disable_rbs(row, bank, sbank, i) == 0); in main()
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Dintel_l3_udev_listener.c105 loc->bank = atoi(udev_device_get_property_value(udev_dev, "BANK")); in l3_listen()
112 loc->slice, loc->row, loc->bank, loc->subbank, in l3_listen()
113 loc->row, loc->bank, loc->subbank, loc->slice) != -1); in l3_listen()
Dintel_l3_parity.h17 uint8_t bank; member
/external/arm-trusted-firmware/drivers/st/bsec/
Dbsec.c127 uint32_t bank = otp_bank_offset(otp); in bsec_check_error() local
129 if ((mmio_read_32(bsec_base + BSEC_DISTURBED_OFF + bank) & bit) != 0U) { in bsec_check_error()
133 if ((mmio_read_32(bsec_base + BSEC_ERROR_OFF + bank) & bit) != 0U) { in bsec_check_error()
577 uint32_t bank = otp_bank_offset(otp); in bsec_write_sr_lock() local
583 bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank); in bsec_write_sr_lock()
605 mmio_write_32(bsec_base + BSEC_SRLOCK_OFF + bank, bank_value); in bsec_write_sr_lock()
621 uint32_t bank = otp_bank_offset(otp); in bsec_read_sr_lock() local
623 uint32_t bank_value = mmio_read_32(bsec_base + BSEC_SRLOCK_OFF + bank); in bsec_read_sr_lock()
638 uint32_t bank = otp_bank_offset(otp); in bsec_write_sw_lock() local
644 bank_value = mmio_read_32(bsec_base + BSEC_SWLOCK_OFF + bank); in bsec_write_sw_lock()
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/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/
Drk3399_gpio.c163 uint32_t bank = GET_GPIO_BANK(gpio); in get_pull() local
167 assert((port < 5) && (bank < 4)); in get_pull()
173 port * 16 + bank * 4); in get_pull()
177 (port - 2) * 16 + bank * 4); in get_pull()
190 if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) { in get_pull()
205 uint32_t bank = GET_GPIO_BANK(gpio); in set_pull() local
209 assert((port < 5) && (bank < 4)); in set_pull()
221 if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) { in set_pull()
232 port * 16 + bank * 4, in set_pull()
236 (port - 2) * 16 + bank * 4, in set_pull()
/external/mesa3d/src/amd/addrlib/src/r800/
Degbaddrlib.cpp1611 UINT_32 bank; in ComputeSurfaceAddrFromCoordMacroTiled() local
1806 bank = ComputeBankFromCoord(x, in ComputeSurfaceAddrFromCoordMacroTiled()
1832 UINT_32 bankBits = bank << (numPipeInterleaveBits + numPipeBits + in ComputeSurfaceAddrFromCoordMacroTiled()
2349 UINT_32 bank; in ComputeSurfaceCoordFromAddrMacroTiled() local
2446 bank = ComputeBankFromAddr(addr, banks, pipes); in ComputeSurfaceCoordFromAddrMacroTiled()
2453 bank, in ComputeSurfaceCoordFromAddrMacroTiled()
2477 UINT_32 bank, ///< [in] bank number in ComputeSurfaceCoord2DFromBankPipe() argument
2526 bank ^= tileSplitRotation * tileSlices; in ComputeSurfaceCoord2DFromBankPipe()
2529 bank ^= bankRotation * (slice / microTileThickness) + bankSwizzle; in ComputeSurfaceCoord2DFromBankPipe()
2530 bank %= pTileInfo->banks; in ComputeSurfaceCoord2DFromBankPipe()
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/external/arm-trusted-firmware/drivers/st/fmc/
Dstm32_fmc2_nand.c808 uint8_t bank; in stm32_fmc2_init() local
839 bank = fdt32_to_cpu(*cuint); in stm32_fmc2_init()
840 if ((bank >= MAX_BANK) || ((bank_assigned & BIT(bank)) != 0U)) { in stm32_fmc2_init()
843 bank_assigned |= BIT(bank); in stm32_fmc2_init()
844 bank_address[bank] = fdt32_to_cpu(*(cuint + 2)); in stm32_fmc2_init()
870 bank = fdt32_to_cpu(*cuint); in stm32_fmc2_init()
871 if (bank >= MAX_BANK) { in stm32_fmc2_init()
875 bank_address[bank]; in stm32_fmc2_init()
877 bank = fdt32_to_cpu(*(cuint + 3)); in stm32_fmc2_init()
878 if (bank >= MAX_BANK) { in stm32_fmc2_init()
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/external/arm-trusted-firmware/fdts/
Dstm32mp151.dtsi490 st,bank-name = "GPIOA";
501 st,bank-name = "GPIOB";
512 st,bank-name = "GPIOC";
523 st,bank-name = "GPIOD";
534 st,bank-name = "GPIOE";
545 st,bank-name = "GPIOF";
556 st,bank-name = "GPIOG";
567 st,bank-name = "GPIOH";
578 st,bank-name = "GPIOI";
589 st,bank-name = "GPIOJ";
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/external/brotli/c/enc/
Dhash_forgetful_chain_inc.h138 const size_t bank = key & (NUM_BANKS - 1); in FN() local
139 const size_t idx = self->free_slot_idx[bank]++ & (BANK_SIZE - 1); in FN()
143 banks[bank].slots[idx].delta = (uint16_t)delta; in FN()
144 banks[bank].slots[idx].next = head[key]; in FN()
243 const size_t bank = key & (NUM_BANKS - 1); in FN() local
254 slot = banks[bank].slots[last].next; in FN()
255 delta = banks[bank].slots[last].delta; in FN()
/external/arm-trusted-firmware/include/drivers/st/
Dstm32_gpio.h52 void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
54 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure);
/external/tpm2-tss/src/tss2-fapi/
Difapi_helpers.c1884 TPMI_ALG_HASH bank, in ifapi_extend_vpcr() argument
1895 if (event->digests.digests[i].hashAlg == bank) { in ifapi_extend_vpcr()
1901 r = ifapi_crypto_hash_start(&cryptoContext, bank); in ifapi_extend_vpcr()
1914 LOG_ERROR("No digest for bank %"PRIu16" found in event", bank); in ifapi_extend_vpcr()
1956 TPMI_ALG_HASH bank; in ifapi_calculate_pcr_digest() member
1995 pcrs[n_pcrs].bank = pcr_selection->pcrSelections[i].hash; in ifapi_calculate_pcr_digest()
2012 r = ifapi_extend_vpcr(&pcrs[i].value, pcrs[i].bank, &event); in ifapi_calculate_pcr_digest()
2113 UINT32 bank, j; in ifapi_filter_pcr_selection_by_index() local
2126 for (bank = 0; bank < pcr_selection->count; bank++) { in ifapi_filter_pcr_selection_by_index()
2127 if (pcr_selection->pcrSelections[bank].sizeofSelect > 4) { in ifapi_filter_pcr_selection_by_index()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUGenRegisterBankInfo.def172 default: llvm_unreachable("Invalid register bank");
186 default: llvm_unreachable("Invalid register bank");
232 /* FIXME: The generic register bank select does not support complex
235 * FIXME: register bank select now tries to handle complex break downs,
262 // the register bank is SGPR or if we don't know how to handle the vector
/external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_b/
Dboot_init_dram_regdef.h24 #define DBMEMCONF_REG(d3, row, bank, col, dw) \ argument
25 (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
/external/arm-trusted-firmware/drivers/renesas/rzg/ddr/ddr_b/
Dboot_init_dram_regdef.h26 #define DBMEMCONF_REG(d3, row, bank, col, dw) \ argument
27 (((d3) << 30U) | ((row) << 24U) | ((bank) << 16U) | ((col) << 8U) | (dw))
/external/cpuinfo/test/dmesg/
Dpadcod-10.1.log386 <4>[ 7.342935] bank 0 block 0x159,page 0xe0
389 <4>[ 7.344406] bank 0 block 0x14d,page 0xce
392 <4>[ 7.355388] bank 0 block 0x14c,page 0x34
1016 <4>[ 9.323373] bank 0 block 0x14c,page 0x70
1019 <4>[ 9.328592] bank 0 block 0x14c,page 0x6c
1024 <4>[ 9.398126] bank 0 block 0x141,page 0x56
1027 <4>[ 9.401992] bank 0 block 0x13c,page 0x2e
1030 <4>[ 9.409726] bank 0 block 0x13b,page 0xca
1089 <4>[ 12.553923] bank 0 block 0x112,page 0x92
1095 <4>[ 12.816283] bank 0 block 0x110,page 0x1e
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Dnexus4.log156 <6>[ 0.290950] msm_iommu_ctx msm_iommu_ctx.2: context vpe_src using bank 0
157 <6>[ 0.291194] msm_iommu_ctx msm_iommu_ctx.3: context vpe_dst using bank 1
158 <6>[ 0.291500] msm_iommu_ctx msm_iommu_ctx.4: context mdp_port0_cb0 using bank 0
159 <6>[ 0.291835] msm_iommu_ctx msm_iommu_ctx.5: context mdp_port0_cb1 using bank 1
160 <6>[ 0.292079] msm_iommu_ctx msm_iommu_ctx.6: context mdp_port1_cb0 using bank 0
161 <6>[ 0.292415] msm_iommu_ctx msm_iommu_ctx.7: context mdp_port1_cb1 using bank 1
162 <6>[ 0.292720] msm_iommu_ctx msm_iommu_ctx.8: context rot_src using bank 0
163 <6>[ 0.292965] msm_iommu_ctx msm_iommu_ctx.9: context rot_dst using bank 1
164 <6>[ 0.293300] msm_iommu_ctx msm_iommu_ctx.10: context ijpeg_src using bank 0
165 <6>[ 0.293514] msm_iommu_ctx msm_iommu_ctx.11: context ijpeg_dst using bank 1
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/external/arm-trusted-firmware/plat/intel/soc/agilex/soc/
Dagilex_memory_controller.c175 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
191 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + in configure_ddr_sched_ctrl_regs()
194 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
/external/sonivox/arm-wt-22k/lib_src/
Deas_voicemgt.c2568 static EAS_RESULT VMFindProgram (const S_EAS *pEAS, EAS_U32 bank, EAS_U8 programNum, EAS_U16 *pRegi… in VMFindProgram() argument
2582 if (bank == (EAS_U32) pEAS->pBanks[i].locale) in VMFindProgram()
2595 locale = ( bank << 8) | programNum; in VMFindProgram()
2624 static EAS_RESULT VMFindDLSProgram (const S_DLS *pDLS, EAS_U32 bank, EAS_U8 programNum, EAS_U16 *pR… in VMFindDLSProgram() argument
2635 locale = (bank << 8) | programNum; in VMFindDLSProgram()
2679 EAS_U32 bank; in VMProgramChange() local
2688 bank = pChannel->bankNum; in VMProgramChange()
2691 if ((bank & 0xFF00) == DEFAULT_RHYTHM_BANK_NUMBER) in VMProgramChange()
2696 else if ((bank & 0xFF00) == DEFAULT_MELODY_BANK_NUMBER) in VMProgramChange()
2710 prgChg.bank = (EAS_U16) bank; in VMProgramChange()
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/external/arm-trusted-firmware/plat/intel/soc/stratix10/soc/
Ds10_memory_controller.c204 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
220 bank = IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(data) + in configure_ddr_sched_ctrl_regs()
223 ddr_conf = match_ddr_conf(DDR_CONFIG(dram_addr_order, bank, col, row)); in configure_ddr_sched_ctrl_regs()
/external/mesa3d/src/gallium/drivers/r300/
Dr300_fs.c306 unsigned int bank = 0; in r300_emit_fs_code_to_buffer() local
343 unsigned int bank_alu_offset = bank * 64; in r300_emit_fs_code_to_buffer()
345 unsigned int bank_tex_offset = bank * 32; in r300_emit_fs_code_to_buffer()
349 (bank << R400_BANK_SHIFT) | R400_R390_MODE_ENABLE : 0);//2 in r300_emit_fs_code_to_buffer()
383 bank++; in r300_emit_fs_code_to_buffer()
/external/mesa3d/src/freedreno/.gitlab-ci/reference/
Dcrash.log3391 - bank: 0
3393 - bank: 1
3395 - bank: 2
3398 - bank: 0
3400 - bank: 1
3402 - bank: 2
3405 - bank: 0
3407 - bank: 1
3409 - bank: 2
3412 - bank: 0
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