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Searched refs:baseAlign (Results 1 – 14 of 14) sorted by relevance

/external/mesa3d/src/amd/addrlib/src/core/
Daddrlib1.cpp431 ValidBaseAlignments(pOut->baseAlign); in ComputeSurfaceInfo()
900 ValidBaseAlignments(pOut->baseAlign); in ComputeFmaskInfo()
1314 pOut->baseAlign = align; in ComputeHtileInfo()
1335 &pOut->baseAlign); in ComputeHtileInfo()
1340 ValidMetaBaseAlignments(pOut->baseAlign); in ComputeHtileInfo()
1403 &pOut->baseAlign, in ComputeCmaskInfo()
1408 ValidMetaBaseAlignments(pOut->baseAlign); in ComputeCmaskInfo()
1849 UINT_32 baseAlign; in ComputeHtileInfo() local
1877 baseAlign = HwlComputeHtileBaseAlign(flags.tcCompatible, isLinear, pTileInfo); in ComputeHtileInfo()
1885 baseAlign); in ComputeHtileInfo()
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Daddrlib2.cpp320 ValidBaseAlignments(pOut->baseAlign); in ComputeSurfaceInfo()
475 ValidMetaBaseAlignments(pOut->baseAlign); in ComputeHtileInfo()
575 ValidMetaBaseAlignments(pOut->baseAlign); in ComputeCmaskInfo()
710 pOut->baseAlign = localOut.baseAlign; in ComputeFmaskInfo()
719 ValidBaseAlignments(pOut->baseAlign); in ComputeFmaskInfo()
1931 ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0); in ComputeQbStereoInfo()
Daddrlib.cpp409 pOut->baseAlign = m_maxBaseAlign; in GetMaxAlignments()
449 pOut->baseAlign = m_maxMetaBaseAlign; in GetMaxMetaAlignments()
Daddrlib1.h246 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const = 0;
/external/mesa3d/src/amd/addrlib/src/r800/
Dsiaddrlib.h155 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
195 UINT_32 baseAlign, UINT_32 pitchAlign,
226 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
Degbaddrlib.cpp240 &pOut->baseAlign, in ComputeSurfaceInfoLinear()
283 pOut->baseAlign, in ComputeSurfaceInfoLinear()
402 &pOut->baseAlign, in ComputeSurfaceInfoMicroTiled()
431 pOut->baseAlign, in ComputeSurfaceInfoMicroTiled()
955 pOut->baseAlign = in ComputeSurfaceAlignmentsMacroTiled()
1218 *pSizeAlign = out.baseAlign; in HwlGetAlignmentInfoMacroTiled()
3200 UINT_32 baseAlign ///< [in] base alignments in ComputeHtileBytes()
3279 pOut->baseAlign = surfOut.baseAlign; in DispatchComputeFmaskInfo()
4020 UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo); in HwlComputeHtileBaseAlign() local
4027 baseAlign *= pTileInfo->banks; in HwlComputeHtileBaseAlign()
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Degbaddrlib.h173 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
181 UINT_32 baseAlign, UINT_32 pitchAlign,
293 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
Dsiaddrlib.cpp1273 UINT_32 baseAlign ///< [in] base alignments in HwlComputeHtileBytes()
1276 return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign); in HwlComputeHtileBytes()
1686 UINT_32 baseAlign, ///< [in] base alignment in HwlGetSizeAdjustmentLinear() argument
1841 UINT_32 baseAlign, ///< [in] base alignment in HwlGetSizeAdjustmentMicroTiled() argument
1861 while ((physicalSliceSize % baseAlign) != 0) in HwlGetSizeAdjustmentMicroTiled()
1884 while ((logicalSiceSizeStencil % baseAlign) != 0) in HwlGetSizeAdjustmentMicroTiled()
3528 UINT_32 baseAlign = tileSize * pipes * m_tileTable[i].info.banks * in HwlComputeMaxBaseAlignments() local
3531 if (baseAlign > maxBaseAlign) in HwlComputeMaxBaseAlignments()
3533 maxBaseAlign = baseAlign; in HwlComputeMaxBaseAlignments()
3595 pOut->baseAlign *= numMacroTiles; in HwlComputeSurfaceAlignmentsMacroTiled()
Dciaddrlib.cpp2199 UINT_32 baseAlign = tileSize * pipes * m_macroTileTable[i].banks * in HwlComputeMaxBaseAlignments() local
2202 if (baseAlign > maxBaseAlign) in HwlComputeMaxBaseAlignments()
2204 maxBaseAlign = baseAlign; in HwlComputeMaxBaseAlignments()
/external/mesa3d/src/amd/addrlib/src/gfx9/
Dgfx9addrlib.h515 UINT_32 baseAlign; in ComputeSurfaceBaseAlignTiled() local
519 baseAlign = GetBlockSize(swizzleMode); in ComputeSurfaceBaseAlignTiled()
523 baseAlign = 256; in ComputeSurfaceBaseAlignTiled()
526 return baseAlign; in ComputeSurfaceBaseAlignTiled()
Dgfx9addrlib.cpp257 pOut->baseAlign = align; in HwlComputeHtileInfo()
346 pOut->baseAlign = Max(numCompressBlkPerMetaBlk >> 1, sizeAlign); in HwlComputeCmaskInfo()
4103 pOut->baseAlign = ComputeSurfaceBaseAlignTiled(pIn->swizzleMode); in HwlComputeSurfaceInfoTiled()
4115 pOut->baseAlign = Max(pOut->baseAlign, m_pipeInterleaveBytes * m_pipes * m_se); in HwlComputeSurfaceInfoTiled()
4120 pOut->baseAlign = Max(pOut->baseAlign, PrtAlignment); in HwlComputeSurfaceInfoTiled()
4205 … pOut->baseAlign = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? (pIn->bpp / 8) : alignment; in HwlComputeSurfaceInfoLinear()
/external/mesa3d/src/amd/addrlib/inc/
Daddrinterface.h599 UINT_32 baseAlign; ///< Base address alignment member
909 UINT_32 baseAlign; ///< Base alignment member
1128 UINT_32 baseAlign; ///< Base alignment member
1325 UINT_32 baseAlign; ///< Base address alignment member
2326 UINT_32 baseAlign; ///< Maximum base alignment in bytes member
2500 UINT_32 baseAlign; ///< Base address alignment member
2777 UINT_32 baseAlign; ///< Base alignment member
2965 UINT_32 baseAlign; ///< Base alignment member
3174 UINT_32 baseAlign; ///< Base alignment member
/external/mesa3d/src/amd/common/
Dac_surface.c398 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign; in ac_addrlib_create()
539 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign); in gfx6_compute_level()
662 surf->htile_alignment = AddrHtileOut->baseAlign; in gfx6_compute_level()
726 surf->surf_alignment = csio->baseAlign; in gfx6_surface_settings()
1140 surf->fmask_alignment = fout.baseAlign; in gfx6_compute_surface()
1383 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign); in gfx9_compute_miptree()
1384 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign); in gfx9_compute_miptree()
1402 surf->surf_alignment = out.baseAlign; in gfx9_compute_miptree()
1463 surf->htile_alignment = hout.baseAlign; in gfx9_compute_miptree()
1706 surf->fmask_alignment = fout.baseAlign; in gfx9_compute_miptree()
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/external/mesa3d/src/amd/addrlib/src/gfx10/
Dgfx10addrlib.cpp187 pOut->baseAlign = Max(metaBlkSize, 1u << (m_pipesLog2 + 11u)); in HwlComputeHtileInfo()
298 pOut->baseAlign = metaBlkSize; in HwlComputeCmaskInfo()
3161 pOut->baseAlign = blockSize; in ComputeSurfaceInfoMicroTiled()
3266 pOut->baseAlign = blockSize; in ComputeSurfaceInfoMacroTiled()
4396 … pOut->baseAlign = (pIn->swizzleMode == ADDR_SW_LINEAR_GENERAL) ? elementBytes : 256; in HwlComputeSurfaceInfoLinear()