| /external/tensorflow/tensorflow/core/kernels/ |
| D | eigen_spatial_convolutions.h | 38 Index base_idx, Index depth,
44 *block = pad ? Scalar(0) : rhs.coeffNoPadding(depth, base_idx);
57 Index base_idx, Index depth,
65 : rhs.partialPacketNoPadding(depth, base_idx, num_coeffs);
209 const StorageIndex base_idx = lm.baseIndex(start_row, c);
221 Packet p0 = rhs.packetNoPadding(d + 0 * packet_size, base_idx);
222 Packet p1 = rhs.packetNoPadding(d + 1 * packet_size, base_idx);
223 Packet p2 = rhs.packetNoPadding(d + 2 * packet_size, base_idx);
224 Packet p3 = rhs.packetNoPadding(d + 3 * packet_size, base_idx);
237 internal::pstoreu(block, rhs.packetNoPadding(d, base_idx));
[all …]
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| D | eigen_cuboid_convolution.h | 1740 const Index base_idx = lm.baseIndex(p, r, c);
1758 : rhs.packetNoPadding(d, base_idx);
1768 *block = pad ? Scalar(0) : rhs.coeffNoPadding(d, base_idx);
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| /external/arm-trusted-firmware/services/std_svc/sdei/ |
| D | sdei_event.c | 26 unsigned int base_idx; in get_event_entry() local
38 base_idx = plat_my_core_pos() * ((unsigned int) mapping->num_maps); in get_event_entry()
39 cpu_priv_base = &sdei_private_event_table[base_idx]; in get_event_entry()
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| /external/mesa3d/src/amd/common/ |
| D | sid_tables.py | 188 for base_idx in self.name_to_idx.get(array[0].name, []):
189 if base_idx + len(array) > len(self.table):
193 b = self.table[base_idx + i]
197 return base_idx
199 base_idx = len(self.table)
200 self.idxs.add(base_idx)
206 return base_idx
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| /external/tensorflow/tensorflow/core/kernels/image/ |
| D | generate_box_proposals_op.cu.cc | 158 const int base_idx = 4 * i; in WriteUprightBoxesOutput() local
159 d_image_out_rois[base_idx + 0] = box.y; in WriteUprightBoxesOutput()
160 d_image_out_rois[base_idx + 1] = box.x; in WriteUprightBoxesOutput()
161 d_image_out_rois[base_idx + 2] = box.w; in WriteUprightBoxesOutput()
162 d_image_out_rois[base_idx + 3] = box.z; in WriteUprightBoxesOutput()
165 const int base_idx = 4 * i; in WriteUprightBoxesOutput() local
166 d_image_out_rois[base_idx + 0] = 0.; in WriteUprightBoxesOutput()
167 d_image_out_rois[base_idx + 1] = 0.; in WriteUprightBoxesOutput()
168 d_image_out_rois[base_idx + 2] = 0.; in WriteUprightBoxesOutput()
169 d_image_out_rois[base_idx + 3] = 0.; in WriteUprightBoxesOutput()
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| /external/fonttools/Lib/fontTools/varLib/ |
| D | interpolate_layout.py | 39 font = deepcopy(master_fonts[ds.base_idx])
50 assert 0 == model.mapping[ds.base_idx]
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| D | __init__.py | 802 base_idx = None
805 if base_idx is not None:
809 base_idx = i
810 if base_idx is None:
814 log.info("Index of base master: %s", base_idx)
819 base_idx,
896 vf = deepcopy(master_fonts[ds.base_idx])
914 assert 0 == model.mapping[ds.base_idx]
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| /external/webrtc/modules/video_coding/codecs/test/ |
| D | videoprocessor.cc | 563 for (int base_idx = static_cast<int>(spatial_idx) - 1; base_idx >= 0; in BuildAndStoreSuperframe() local
564 --base_idx) { in BuildAndStoreSuperframe()
565 EncodedImage lower_layer = merged_encoded_frames_.at(base_idx); in BuildAndStoreSuperframe()
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| /external/mesa3d/src/compiler/nir/ |
| D | nir_algebraic.py | 427 def __index_comm_exprs(self, base_idx): argument
440 self.comm_expr_idx = base_idx
447 s.__index_comm_exprs(base_idx + self.comm_exprs)
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| /external/llvm-project/compiler-rt/lib/sanitizer_common/ |
| D | sanitizer_allocator_primary64.h | 154 uptr base_idx = region->num_freed_chunks; in GetFromAllocator() local
156 chunks[i] = free_array[base_idx + i]; in GetFromAllocator()
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| /external/mesa3d/src/freedreno/vulkan/ |
| D | tu_shader.c | 275 nir_ssa_def *base_idx = nir_channel(b, intrin->src[buffer_src].ssa, 0); in lower_ssbo_ubo_intrinsic() local
282 nir_if *nif = nir_push_if(b, nir_ieq_imm(b, base_idx, i)); in lower_ssbo_ubo_intrinsic()
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| /external/mesa3d/src/compiler/glsl/ |
| D | ir.cpp | 1910 static const unsigned char base_idx[26] = { in create() local
1951 const unsigned base = base_idx[str[0] - 'a']; in create()
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| /external/virglrenderer/src/ |
| D | vrend_shader.c | 2897 int base_idx = ctx->inputs[input_idx].sid * 4; in create_swizzled_clipdist() local
2901 if (src->Register.Indirect && ((num_clips > 4 && base_idx < num_clips) || num_culls > 4)) in create_swizzled_clipdist()
2908 int idx = base_idx; in create_swizzled_clipdist()
2950 int base_idx = ctx->inputs[input_idx].sid; in load_clipdist_fs() local
2955 snprintf(clip_indirect, 32, "addr%d + %d", src->Indirect.Index, base_idx); in load_clipdist_fs()
2957 snprintf(clip_indirect, 32, "%d + %d", src->Register.Index - offset, base_idx); in load_clipdist_fs()
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