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Searched refs:base_mip (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_meta_resolve_cs.c928 .mipLevel = src_iview->base_mip, in radv_cmd_buffer_resolve_subpass_cs()
934 .mipLevel = dst_iview->base_mip, in radv_cmd_buffer_resolve_subpass_cs()
1006 .baseMipLevel = src_iview->base_mip, in radv_depth_stencil_resolve_subpass_cs()
1022 .baseMipLevel = dst_iview->base_mip, in radv_depth_stencil_resolve_subpass_cs()
1044 range.baseMipLevel = dst_iview->base_mip; in radv_depth_stencil_resolve_subpass_cs()
Dradv_meta_blit.c313 uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip); in meta_emit_blit()
314 uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip); in meta_emit_blit()
315 uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip); in meta_emit_blit()
316 uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip); in meta_emit_blit()
317 uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip); in meta_emit_blit()
Dradv_image.c1536 hw_level = iview->base_mip; in radv_image_view_make_descriptor()
1553 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip]; in radv_image_view_make_descriptor()
1555 base_level_info = &plane->surface.u.legacy.level[iview->base_mip]; in radv_image_view_make_descriptor()
1560 iview->base_mip, in radv_image_view_make_descriptor()
1561 iview->base_mip, in radv_image_view_make_descriptor()
1631 iview->base_mip = range->baseMipLevel; in radv_image_view_init()
Dradv_meta_clear.c733 iview->base_mip == 0 && in depth_view_can_fast_clear()
1724 if (radv_dcc_enabled(iview->image, iview->base_mip)) { in radv_can_fast_clear_color()
1749 uint32_t level = iview->base_mip + l; in radv_can_fast_clear_color()
1779 .baseMipLevel = iview->base_mip, in radv_fast_clear_color()
1797 if (radv_dcc_enabled(iview->image, iview->base_mip)) { in radv_fast_clear_color()
Dradv_meta_resolve.c864 if (radv_dcc_enabled(dst_img, dest_iview->base_mip)) { in radv_cmd_buffer_resolve_subpass()
867 .baseMipLevel = dest_iview->base_mip, in radv_cmd_buffer_resolve_subpass()
Dradv_cmd_buffer.c1668 if (radv_dcc_enabled(image, iview->base_mip)) { in radv_emit_fb_color_state()
1672 .baseMipLevel = iview->base_mip, in radv_emit_fb_color_state()
1717 uint64_t va = radv_get_tc_compat_zrange_va(image, iview->base_mip); in radv_update_zrange_precision()
1957 .baseMipLevel = iview->base_mip, in radv_update_tc_compat_zrange_metadata()
1984 .baseMipLevel = iview->base_mip, in radv_update_ds_clear_metadata()
2016 uint64_t va = radv_get_ds_clear_value_va(image, iview->base_mip); in radv_load_ds_clear_metadata()
2184 .baseMipLevel = iview->base_mip, in radv_update_color_clear_metadata()
2191 radv_dcc_enabled(image, iview->base_mip)); in radv_update_color_clear_metadata()
2209 uint64_t va = radv_image_get_fast_clear_va(image, iview->base_mip); in radv_load_color_clear_metadata()
2212 !radv_dcc_enabled(image, iview->base_mip)) in radv_load_color_clear_metadata()
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Dradv_device.c6665 if (!radv_dcc_enabled(iview->image, iview->base_mip)) in radv_init_dcc_control_reg()
6764 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip]; in radv_initialise_color_surface()
6773 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false); in radv_initialise_color_surface()
6803 if (radv_dcc_enabled(iview->image, iview->base_mip) && in radv_initialise_color_surface()
6805 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset; in radv_initialise_color_surface()
6901 if (radv_dcc_enabled(iview->image, iview->base_mip)) in radv_initialise_color_surface()
6922 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip); in radv_initialise_color_surface()
6928 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip); in radv_initialise_color_surface()
6983 unsigned level = iview->base_mip; in radv_initialise_ds_surface()
Dradv_private.h2103 uint32_t base_mip; member
/external/mesa3d/docs/relnotes/
D17.2.1.rst68 - radv/gfx9: set descriptor up for base_mip to level range.