Home
last modified time | relevance | path

Searched refs:base_reg (Results 1 – 25 of 35) sorted by relevance

12

/external/boringssl/src/crypto/test/asm/
Dtrampoline-ppc.pl52 my ($op, $base_reg, $base_offset) = @_;
58 $code .= "\t${op}vx\tv$_, r11, $base_reg\n";
63 $code .= "\t${op}d\tr$_, $offset($base_reg)\n";
68 $code .= "\t${op}fd\tf$_, $offset($base_reg)\n";
73 my ($base_reg, $base_offset) = @_;
74 load_or_store_regs("l", $base_reg, $base_offset);
78 my ($base_reg, $base_offset) = @_;
79 load_or_store_regs("st", $base_reg, $base_offset);
/external/arm-trusted-firmware/plat/marvell/armada/a3k/common/
Ddram_win.c189 uint32_t base_reg, ctrl_reg, size_reg, enabled, target; in dram_win_map_build() local
202 base_reg = mmio_read_32(CPU_DEC_WIN_BASE_REG(win_id)); in dram_win_map_build()
205 win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> in dram_win_map_build()
225 uint32_t base_reg, ctrl_reg, size_reg, remap_reg; in cpu_win_set() local
237 base_reg = (uint32_t)(win_cfg->base_addr / in cpu_win_set()
239 base_reg <<= CPU_DEC_BR_BASE_OFFS; in cpu_win_set()
240 base_reg &= CPU_DEC_BR_BASE_MASK; in cpu_win_set()
241 mmio_write_32(CPU_DEC_WIN_BASE_REG(win_id), base_reg); in cpu_win_set()
/external/llvm-project/lldb/include/lldb/Core/
DEmulateInstruction.h194 RegisterInfo base_reg; // base register number member
200 RegisterInfo base_reg; // base register for address calculation member
205 RegisterInfo base_reg; // base register for address calculation member
242 void SetRegisterPlusOffset(RegisterInfo base_reg, int64_t signed_offset) { in SetRegisterPlusOffset()
244 info.RegisterPlusOffset.reg = base_reg; in SetRegisterPlusOffset()
248 void SetRegisterPlusIndirectOffset(RegisterInfo base_reg, in SetRegisterPlusIndirectOffset()
251 info.RegisterPlusIndirectOffset.base_reg = base_reg; in SetRegisterPlusIndirectOffset()
256 RegisterInfo base_reg, in SetRegisterToRegisterPlusOffset()
260 info.RegisterToRegisterPlusOffset.base_reg = base_reg; in SetRegisterToRegisterPlusOffset()
264 void SetRegisterToRegisterPlusIndirectOffset(RegisterInfo base_reg, in SetRegisterToRegisterPlusIndirectOffset()
[all …]
/external/capstone/contrib/objdump/
Dobjdump-m68k.py133 str = dump_op_reg(insn, op.mem.base_reg)
157 …str = dump_op_reg(insn, op.mem.base_reg) + "@(" + "{0:016x}".format(disp) + "," + dump_op_reg(insn…
164 str += format("%s" % ( dump_op_reg(insn, op.mem.base_reg) ))
186 if op.mem.base_reg != M68K_REG_INVALID:
187 str += format("a%d,%s" % ( op.mem.base_reg - M68K_REG_A0, s_spacing))
206 if op.mem.base_reg:
207 str += format("%s" % ( dump_op_reg(insn, op.mem.base_reg) ))
219 if op.mem.base_reg != M68K_REG_INVALID:
221 str += format(",%s%s" % ( s_spacing, dump_op_reg(insn, op.mem.base_reg)))
223 str += format("%s" % ( dump_op_reg(insn, op.mem.base_reg)))
[all …]
/external/capstone/arch/M68K/
DM68KInstPrinter.c155 … "%s$%x(a%d)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), (op->mem.base_reg - M68K_REG_A0)); … in printAddressingMode()
181 …c)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), getRegName(op->mem.base_reg), s_spacing, getR… in printAddressingMode()
198 if (op->mem.base_reg != M68K_REG_INVALID) in printAddressingMode()
199 SStream_concat(O, "a%d,%s", op->mem.base_reg - M68K_REG_A0, s_spacing); in printAddressingMode()
224 if (op->mem.base_reg != M68K_REG_INVALID) { in printAddressingMode()
226 SStream_concat(O, ",%s%s", s_spacing, getRegName(op->mem.base_reg)); in printAddressingMode()
228 SStream_concat(O, "%s", getRegName(op->mem.base_reg)); in printAddressingMode()
/external/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp4534 RegisterInfo base_reg; in EmulateLDRRtRnImm() local
4535 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + Rn, base_reg); in EmulateLDRRtRnImm()
4543 ctx.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base)); in EmulateLDRRtRnImm()
4546 ctx.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base)); in EmulateLDRRtRnImm()
4557 context.SetRegisterPlusOffset(base_reg, (int32_t)(offset_addr - base)); in EmulateLDRRtRnImm()
4670 RegisterInfo base_reg; in EmulateSTM() local
4671 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); in EmulateSTM()
4694 context.SetRegisterToRegisterPlusOffset(data_reg, base_reg, offset); in EmulateSTM()
4792 RegisterInfo base_reg; in EmulateSTMDA() local
4793 GetRegisterInfo(eRegisterKindDWARF, dwarf_r0 + n, base_reg); in EmulateSTMDA()
[all …]
/external/capstone/cstool/
Dcstool_m680x.c112 if (op->idx.base_reg != M680X_REG_INVALID) in print_insn_detail_m680x()
114 cs_reg_name(handle, op->idx.base_reg)); in print_insn_detail_m680x()
125 if (op->idx.base_reg == M680X_REG_PC) in print_insn_detail_m680x()
Dcstool_m68k.c94 if (op->mem.base_reg != M68K_REG_INVALID) in print_insn_detail_m68k()
96 i, cs_reg_name(handle, op->mem.base_reg)); in print_insn_detail_m68k()
/external/capstone/suite/cstest/src/
Dm680x_detail.c98 if (op->idx.base_reg != M680X_REG_INVALID) in get_detail_m680x()
99 add_str(&result, " ; base register: %s", cs_reg_name(*handle, op->idx.base_reg)); in get_detail_m680x()
109 if (op->idx.base_reg == M680X_REG_PC) in get_detail_m680x()
Dm68k_detail.c91 if (op->mem.base_reg != M68K_REG_INVALID) in get_detail_m68k()
92 … add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base_reg)); in get_detail_m68k()
/external/capstone/bindings/python/
Dtest_m680x.py93 if i.idx.base_reg != M680X_REG_INVALID:
94 print("\t\t\tbase register: %s" % insn.reg_name(i.idx.base_reg))
99 if i.idx.base_reg == M680X_REG_PC:
Dtest_m68k.py68 if op.mem.base_reg != M68K_REG_INVALID:
69 print("\t\t\toperands[%u].mem.base: REG = %s" % (i, insn.reg_name(op.mem.base_reg)))
/external/mesa3d/src/util/
Dregister_allocate.h60 unsigned int base_reg, unsigned int reg);
64 unsigned int base_reg, unsigned int reg0, unsigned int reg1);
Dregister_allocate.c282 unsigned int base_reg, unsigned int reg) in ra_add_transitive_reg_conflict() argument
284 ra_add_reg_conflict(regs, reg, base_reg); in ra_add_transitive_reg_conflict()
286 util_dynarray_foreach(&regs->regs[base_reg].conflict_list, unsigned int, in ra_add_transitive_reg_conflict()
301 unsigned int base_reg, unsigned int reg0, unsigned int reg1) in ra_add_transitive_reg_pair_conflict() argument
303 ra_add_reg_conflict(regs, reg0, base_reg); in ra_add_transitive_reg_pair_conflict()
304 ra_add_reg_conflict(regs, reg1, base_reg); in ra_add_transitive_reg_pair_conflict()
306 util_dynarray_foreach(&regs->regs[base_reg].conflict_list, unsigned int, i) { in ra_add_transitive_reg_pair_conflict()
/external/capstone/arch/M680X/
DM680XInstPrinter.c181 if (op->idx.base_reg == M680X_REG_PC) in printOperand()
195 printRegName(MI->csh, O, op->idx.base_reg); in printOperand()
197 if (op->idx.base_reg == M680X_REG_PC && in printOperand()
DM680XDisassembler.c355 add_reg_to_rw_list(MI, op->idx.base_reg, READ); in update_am_reg_list()
357 if (op->idx.base_reg == M680X_REG_X && in update_am_reg_list()
366 add_reg_to_rw_list(MI, op->idx.base_reg, WRITE); in update_am_reg_list()
368 if (op->idx.base_reg == M680X_REG_X && in update_am_reg_list()
1198 static void add_indexed_operand(m680x_info *info, m680x_reg base_reg, in add_indexed_operand() argument
1207 op->idx.base_reg = base_reg; in add_indexed_operand()
1257 op->idx.base_reg = g_rr5_to_reg_ids[(post_byte >> 5) & 0x03]; in indexed09_hdlr()
1312 op->idx.base_reg = M680X_REG_PC; in indexed09_hdlr()
1328 op->idx.base_reg = M680X_REG_PC; in indexed09_hdlr()
1357 op->idx.base_reg = M680X_REG_INVALID; in indexed09_hdlr()
[all …]
/external/capstone/tests/
Dtest_m680x.c138 if (op->idx.base_reg != M680X_REG_INVALID) in print_insn_detail()
140 cs_reg_name(handle, op->idx.base_reg)); in print_insn_detail()
151 if (op->idx.base_reg == M680X_REG_PC) in print_insn_detail()
Dtest_m68k.c114 if (op->mem.base_reg != M68K_REG_INVALID) in print_insn_detail()
116 i, cs_reg_name(handle, op->mem.base_reg)); in print_insn_detail()
/external/capstone/bindings/java/
DTestM680x.java95 if (i.value.idx.base_reg != M680X_REG_INVALID) { in print_ins_detail()
96 String regName = ins.regName(i.value.idx.base_reg); in print_ins_detail()
109 if (i.value.idx.base_reg == M680X_REG_PC) in print_ins_detail()
/external/mesa3d/src/intel/compiler/
Dbrw_vec4_reg_allocate.cpp138 for (int base_reg = j; in brw_vec4_alloc_reg_set() local
139 base_reg < j + class_sizes[i]; in brw_vec4_alloc_reg_set()
140 base_reg++) { in brw_vec4_alloc_reg_set()
141 ra_add_reg_conflict(compiler->vec4_reg_set.regs, base_reg, reg); in brw_vec4_alloc_reg_set()
Dbrw_fs_reg_allocate.cpp228 for (int base_reg = j; in brw_alloc_reg_set() local
229 base_reg < j + (class_sizes[i] + 1) / 2; in brw_alloc_reg_set()
230 base_reg++) { in brw_alloc_reg_set()
231 ra_add_reg_conflict(regs, base_reg, reg); in brw_alloc_reg_set()
242 for (int base_reg = j; in brw_alloc_reg_set() local
243 base_reg < j + class_sizes[i]; in brw_alloc_reg_set()
244 base_reg++) { in brw_alloc_reg_set()
245 ra_add_reg_conflict(regs, base_reg, reg); in brw_alloc_reg_set()
/external/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
DPdbUtil.cpp637 RegisterId base_reg = in GetVariableLocationInfo() local
640 if (base_reg == RegisterId::VFRAME) { in GetVariableLocationInfo()
651 MakeRegRelLocationExpression(base_reg, loc.Hdr.Offset, module); in GetVariableLocationInfo()
661 RegisterId base_reg = (RegisterId)(uint16_t)loc.Hdr.Register; in GetVariableLocationInfo() local
663 if (base_reg == RegisterId::VFRAME) { in GetVariableLocationInfo()
674 base_reg, loc.Hdr.BasePointerOffset, module); in GetVariableLocationInfo()
/external/capstone/bindings/ocaml/
Dm680x.ml9 base_reg: int; RecordField
/external/capstone/bindings/java/capstone/
DM680x.java17 public int base_reg; field in M680x.OpIndexed
/external/llvm-project/lldb/source/Core/
DEmulateInstruction.cpp453 info.RegisterPlusIndirectOffset.base_reg.name, in Dump()
459 info.RegisterToRegisterPlusOffset.base_reg.name, in Dump()
466 info.RegisterToRegisterPlusIndirectOffset.base_reg.name, in Dump()

12