| /external/libhevc/decoder/ |
| D | ihevcd_debug.h | 150 …, qp_q, beta_offset_div2, tc_offset_div2, filter_p, filter_q) ihevcd_debug_deblk_luma_vert(pu1_src… argument
151 …, qp_q, beta_offset_div2, tc_offset_div2, filter_p, filter_q) ihevcd_debug_deblk_luma_horz(pu1_src… argument
157 #define DUMP_DEBLK_LUMA_VERT(pu1_src, src_strd, u4_bs3, qp_p, qp_q, beta_offset_div2, tc_offset_div… argument
158 #define DUMP_DEBLK_LUMA_HORZ(pu1_src, src_strd, u4_bs3, qp_p, qp_q, beta_offset_div2, tc_offset_div… argument
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| /external/libhevc/common/ |
| D | ihevc_deblk.h | 47 WORD32 beta_offset_div2,
58 WORD32 beta_offset_div2,
91 WORD32 beta_offset_div2,
103 WORD32 beta_offset_div2,
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| D | ihevc_deblk_edge_filter.c | 103 WORD32 beta_offset_div2, in ihevc_deblk_luma_vert() argument
121 beta_indx = CLIP3(qp_luma + (beta_offset_div2 << 1), 0, 51); in ihevc_deblk_luma_vert()
340 WORD32 beta_offset_div2, in ihevc_deblk_luma_horz() argument
358 beta_indx = CLIP3(qp_luma + (beta_offset_div2 << 1), 0, 51); in ihevc_deblk_luma_horz()
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| D | ihevc_hbd_deblk_edge_filter.c | 109 WORD32 beta_offset_div2, in ihevc_hbd_deblk_luma_vert() argument
128 beta_indx = CLIP3(qp_luma + (beta_offset_div2 << 1), 0, 51); in ihevc_hbd_deblk_luma_vert()
344 WORD32 beta_offset_div2, in ihevc_hbd_deblk_luma_horz() argument
363 beta_indx = CLIP3(qp_luma + (beta_offset_div2 << 1), 0, 51); in ihevc_hbd_deblk_luma_horz()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | radeon_vcn_enc.h | 302 int32_t beta_offset_div2; member
310 int32_t beta_offset_div2; member
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| D | radeon_vcn_enc_2_0.c | 96 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_loop_filter_hevc()
241 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_nalu_pps_hevc()
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| D | radeon_vcn_enc_1_2.c | 243 enc->enc_pic.h264_deblock.beta_offset_div2 = 0; in radeon_enc_deblocking_filter_h264()
250 RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2); in radeon_enc_deblocking_filter_h264()
261 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_deblocking_filter_hevc()
530 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_nalu_pps_hevc()
740 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2); in radeon_enc_slice_header()
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| D | radeon_vcn_enc_3_0.c | 156 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_nalu_pps_hevc()
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| D | radeon_uvd_enc.h | 270 int32_t beta_offset_div2; member
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| D | radeon_uvd_enc_1_1.c | 362 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2; in radeon_uvd_enc_deblocking_filter_hevc()
370 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_uvd_enc_deblocking_filter_hevc()
528 radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_uvd_enc_nalu_pps_hevc()
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| D | radeon_vcn_enc.c | 155 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2; in radeon_vcn_enc_get_param()
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| /external/libhevc/common/x86/ |
| D | ihevc_deblk_ssse3_intr.c | 105 WORD32 beta_offset_div2, in ihevc_deblk_luma_vert_ssse3() argument
129 beta_indx = CLIP3(qp_luma + (beta_offset_div2 << 1), 0, 51); in ihevc_deblk_luma_vert_ssse3()
541 WORD32 beta_offset_div2, in ihevc_deblk_luma_horz_ssse3() argument
569 beta_indx = CLIP3(qp_luma + (beta_offset_div2 << 1), 0, 51); in ihevc_deblk_luma_horz_ssse3()
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| /external/libhevc/common/arm/ |
| D | ihevc_deblk_luma_vert.s | 96 @ beta_indx = clip3(qp_luma + (beta_offset_div2 << 1), 0, 51)@
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| D | ihevc_deblk_luma_horz.s | 94 @ beta_indx = clip3(qp_luma + (beta_offset_div2 << 1), 0, 51)@
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