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Searched refs:brtarget (Results 1 – 25 of 80) sorted by relevance

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/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td68 (BCOND brtarget:$imm, condVal)>;
72 (BCONDA brtarget:$imm, condVal)>;
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td67 (BCOND brtarget:$imm, condVal)>;
71 (BCONDA brtarget:$imm, condVal)>;
75 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
79 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
83 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
87 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
91 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
95 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
99 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
103 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
DSparcInstrInfo.td151 def brtarget : Operand<OtherVT> {
782 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
832 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
835 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
872 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
875 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
895 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
898 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td67 (BCOND brtarget:$imm, condVal)>;
71 (BCONDA brtarget:$imm, condVal)>;
75 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
79 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
83 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
87 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
91 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
95 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
99 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
103 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
DSparcInstrInfo.td151 def brtarget : Operand<OtherVT> {
782 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
832 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
835 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
872 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
875 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
895 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
898 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
/external/capstone/arch/Sparc/
DSparcGenAsmWriter.inc1232 // (BCOND brtarget:$imm, 8)
1239 // (BCOND brtarget:$imm, 0)
1246 // (BCOND brtarget:$imm, 9)
1253 // (BCOND brtarget:$imm, 1)
1260 // (BCOND brtarget:$imm, 10)
1267 // (BCOND brtarget:$imm, 2)
1274 // (BCOND brtarget:$imm, 11)
1281 // (BCOND brtarget:$imm, 3)
1288 // (BCOND brtarget:$imm, 12)
1295 // (BCOND brtarget:$imm, 4)
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td83 class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
84 class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
85 class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
86 class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
87 class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
88 class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
89 class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
90 class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
91 class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
92 class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
DMips32r6InstrInfo.td418 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
433 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
434 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
435 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
436 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
438 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
439 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
441 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
442 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
444 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
[all …]
DMips64InstrInfo.td266 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>,
268 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>,
270 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>,
272 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>,
274 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>,
276 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>,
431 PseudoSE<(outs GPR64Opnd:$dst), (ins brtarget:$tgt), []>, GPR_64 {
436 PseudoSE<(outs GPR64Opnd:$dst), (ins GPR64Opnd:$src, brtarget:$tgt), []>,
445 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>,
512 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
[all …]
DMipsInstrInfo.td837 def brtarget : Operand<OtherVT> {
1544 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
1994 (ins brtarget:$tgt, brtarget:$baltgt), []> {
1999 (ins brtarget:$tgt), []> {
2005 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []> {
2010 (ins GPR32Opnd:$src, brtarget:$tgt), []> {
2219 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>,
2221 def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
2223 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>,
2225 def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>,
[all …]
DMipsInstrFPU.td697 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
699 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
701 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
703 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
882 (BCTrue FCC0, brtarget:$offset), 1>;
885 (BCFalse FCC0, brtarget:$offset), 1>;
/external/llvm-project/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td83 class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
84 class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
85 class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
86 class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
87 class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
88 class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
89 class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
90 class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
91 class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
92 class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
DMips32r6InstrInfo.td418 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
433 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
434 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
435 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
436 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
438 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
439 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
441 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
442 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
444 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
[all …]
DMipsInstrInfo.td837 def brtarget : Operand<OtherVT> {
1544 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
1995 (ins brtarget:$tgt, brtarget:$baltgt), []> {
2000 (ins brtarget:$tgt), []> {
2006 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []> {
2011 (ins GPR32Opnd:$src, brtarget:$tgt), []> {
2220 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>,
2222 def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
2224 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>,
2226 def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>,
[all …]
DMips64InstrInfo.td266 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>,
268 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>,
270 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>,
272 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>,
274 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>,
276 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>,
431 PseudoSE<(outs GPR64Opnd:$dst), (ins brtarget:$tgt), []>, GPR_64 {
436 PseudoSE<(outs GPR64Opnd:$dst), (ins GPR64Opnd:$src, brtarget:$tgt), []>,
445 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>,
512 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
[all …]
DMipsInstrFPU.td730 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
732 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
734 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
736 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
915 (BCTrue FCC0, brtarget:$offset), 1>;
918 (BCFalse FCC0, brtarget:$offset), 1>;
/external/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td380 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
395 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
396 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
397 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
398 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
400 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
401 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
403 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
404 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
406 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
[all …]
DMips64InstrInfo.td236 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
237 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
238 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
239 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
240 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
241 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
347 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
410 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
412 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64,
416 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
[all …]
DMipsInstrInfo.td626 def brtarget : Operand<OtherVT> {
1303 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
1304 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
1366 PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
1367 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
1658 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1662 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1860 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1861 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1863 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
[all …]
DMipsInstrFPU.td528 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
530 def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
532 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
534 def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
593 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
595 def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
597 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
599 def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td46 def brtarget : Operand<OtherVT>;
83 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
104 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
353 : InstBPF<(outs), (ins brtarget:$BrDst),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td57 def brtarget : Operand<OtherVT> {
160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
192 (ins GPR32:$dst, GPR32:$src, brtarget:$BrDst),
208 (ins GPR32:$dst, i32imm:$imm, brtarget:$BrDst),
471 (ins brtarget:$BrDst),
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenInstrInfo.inc10610 brtarget = 3,
13875 OpTypes::brtarget,
13876 OpTypes::brtarget,
13878 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget,
13879 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget,
13880 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget,
13881 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget,
13882 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget,
13883 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget,
13884 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget,
[all …]
/external/llvm-project/llvm/lib/Target/BPF/
DBPFInstrInfo.td57 def brtarget : Operand<OtherVT> {
160 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
176 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
192 (ins GPR32:$dst, GPR32:$src, brtarget:$BrDst),
208 (ins GPR32:$dst, i32imm:$imm, brtarget:$BrDst),
471 (ins brtarget:$BrDst),
/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td475 (J2_jumpf PredRegs:$Pu, brtarget:$r15_2)>,
480 (J2_jumpt PredRegs:$Pu, brtarget:$r15_2)>,
484 (J2_jumpt PredRegs:$src, brtarget:$r15_2), 0>;
487 (J2_jumpf PredRegs:$src, brtarget:$r15_2), 0>;

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