/external/mesa3d/src/intel/compiler/ |
D | brw_clip_line.c | 64 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_line_alloc_regs() 65 c->reg.t0 = brw_vec1_grf(i, 1); in brw_clip_line_alloc_regs() 66 c->reg.t1 = brw_vec1_grf(i, 2); in brw_clip_line_alloc_regs() 67 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_line_alloc_regs() 71 c->reg.dp0 = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_line_alloc_regs() 72 c->reg.dp1 = brw_vec1_grf(i, 4); in brw_clip_line_alloc_regs() 80 c->reg.vertex_src_mask = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); in brw_clip_line_alloc_regs() 81 c->reg.clipdistance_offset = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_W); in brw_clip_line_alloc_regs() 85 c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); in brw_clip_line_alloc_regs()
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D | brw_compile_sf.c | 286 c->pv = retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_D); in alloc_regs() 287 c->det = brw_vec1_grf(1, 2); in alloc_regs() 288 c->dx0 = brw_vec1_grf(1, 3); in alloc_regs() 289 c->dx2 = brw_vec1_grf(1, 4); in alloc_regs() 290 c->dy0 = brw_vec1_grf(1, 5); in alloc_regs() 291 c->dy2 = brw_vec1_grf(1, 6); in alloc_regs() 295 c->z[0] = brw_vec1_grf(2, 0); in alloc_regs() 296 c->inv_w[0] = brw_vec1_grf(2, 1); in alloc_regs() 297 c->z[1] = brw_vec1_grf(2, 2); in alloc_regs() 298 c->inv_w[1] = brw_vec1_grf(2, 3); in alloc_regs() [all …]
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D | test_eu_compact.cpp | 226 struct brw_reg g0 = brw_vec1_grf(0, 0); in gen_ADD_vec1_GRF_GRF_GRF() 227 struct brw_reg g2 = brw_vec1_grf(2, 0); in gen_ADD_vec1_GRF_GRF_GRF() 228 struct brw_reg g4 = brw_vec1_grf(4, 0); in gen_ADD_vec1_GRF_GRF_GRF() 237 struct brw_reg interp = brw_vec1_grf(2, 0); in gen_PLN_MRF_GRF_GRF()
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D | brw_clip_tri.c | 82 c->reg.t = brw_vec1_grf(i, 0); in brw_clip_tri_alloc_regs() 83 c->reg.loopcount = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_D); in brw_clip_tri_alloc_regs() 84 c->reg.nr_verts = retype(brw_vec1_grf(i, 2), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs() 85 c->reg.planemask = retype(brw_vec1_grf(i, 3), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs() 89 c->reg.dpPrev = brw_vec1_grf(i, 0); /* fixme - dp4 will clobber r.1,2,3 */ in brw_clip_tri_alloc_regs() 90 c->reg.dp = brw_vec1_grf(i, 4); in brw_clip_tri_alloc_regs() 116 c->reg.vertex_src_mask = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs() 117 c->reg.clipdistance_offset = retype(brw_vec1_grf(i, 1), BRW_REGISTER_TYPE_W); in brw_clip_tri_alloc_regs() 121 c->reg.ff_sync = retype(brw_vec1_grf(i, 0), BRW_REGISTER_TYPE_UD); in brw_clip_tri_alloc_regs()
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D | brw_fs_visitor.cpp | 158 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gen4() 177 const fs_reg xstart(negate(brw_vec1_grf(1, 0))); in emit_interpolation_setup_gen4() 178 const fs_reg ystart(negate(brw_vec1_grf(1, 1))); in emit_interpolation_setup_gen4() 279 struct brw_reg gi_uw = retype(brw_vec1_grf(1 + i, 0), BRW_REGISTER_TYPE_UW); in emit_interpolation_setup_gen6() 354 retype(brw_vec1_grf(1 + i, 7), BRW_REGISTER_TYPE_UW)); in emit_interpolation_setup_gen6() 890 fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD)); in emit_barrier()
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D | brw_reg.h | 772 brw_vec1_grf(unsigned nr, unsigned subnr) in brw_vec1_grf() function 1153 struct brw_reg reg = brw_vec1_grf(0, 0); in brw_vec1_indirect() 1163 struct brw_reg reg = brw_vec1_grf(0, 0); in brw_VxH_indirect()
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D | brw_vec4_generator.cpp | 820 struct brw_reg index_reg = brw_vec1_grf( in generate_tcs_input_urb_offsets() 883 struct brw_reg urb_handle = brw_vec1_grf(0, 0); in generate_tcs_output_urb_offsets() 914 retype(brw_vec1_grf(1, 3), BRW_REGISTER_TYPE_UD), in generate_tes_create_input_read_header() 1021 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)); in generate_tcs_thread_end() 1042 brw_MOV(p, dst, retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_D)); in generate_tes_get_primitive_id() 1051 brw_MOV(p, dst, retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD)); in generate_tcs_get_primitive_id() 1074 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), in generate_tcs_create_barrier_header()
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D | brw_fs.cpp | 1300 fs_reg g1 = fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W)); in emit_frontfacing_interpolation() 1317 fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W)); in emit_frontfacing_interpolation() 1332 fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D)); in emit_frontfacing_interpolation() 1449 stride(retype(brw_vec1_grf(1 + i, 0), BRW_REGISTER_TYPE_UB), in emit_sampleid_setup() 1483 .AND(t1, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)), in emit_sampleid_setup() 1648 struct brw_reg brw_reg = brw_vec1_grf(payload.num_regs + in assign_curb_setup() 1670 struct brw_reg mask = brw_vec1_grf(payload.num_regs + mask_param / 8, in assign_curb_setup() 4301 return retype(brw_vec1_grf((bld.group() >= 16 ? 2 : 1), 7), in sample_mask_reg() 4402 .MOV(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW), in lower_fb_write_logical_send() 4454 retype(brw_vec1_grf(0, 0), in lower_fb_write_logical_send() [all …]
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D | brw_fs_nir.cpp | 221 stride(retype(brw_vec1_grf(1 + i, 7), in emit_system_values_block() 592 fs_reg g1 = fs_reg(retype(brw_vec1_grf(1, 1), BRW_REGISTER_TYPE_W)); in optimize_frontfacing_ternary() 609 fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W)); in optimize_frontfacing_ternary() 630 fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D)); in optimize_frontfacing_ternary() 2487 retype(brw_vec1_grf(first_icp_handle + vertex / 8, vertex % 8), in emit_gs_input_load() 2632 retype(brw_vec1_grf(1 + (vertex >> 3), vertex & 7), in get_tcs_single_patch_icp_handle() 2721 return retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD); in get_tcs_output_urb_handle() 2747 : brw_vec1_grf(0, 1))); in nir_emit_tcs_intrinsic() 2771 chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), in nir_emit_tcs_intrinsic() 2777 chanbld.AND(m0_2, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD), in nir_emit_tcs_intrinsic() [all …]
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D | brw_fs_generator.cpp | 424 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD), in generate_fb_write() 1576 retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD), in generate_scratch_header() 1585 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), in generate_scratch_header() 1839 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0), in generate_shader_time_add() 1841 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0), in generate_shader_time_add()
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D | gen6_gs_visitor.cpp | 109 src_reg(retype(brw_vec1_grf(1, 4), BRW_REGISTER_TYPE_UD)))); in emit_prolog()
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D | test_eu_validate.cpp | 700 struct brw_reg g0_0 = brw_vec1_grf(0, 0); in TEST_P() 1102 struct brw_reg g0_0 = brw_vec1_grf(0, 0); in TEST_P()
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D | brw_eu_emit.c | 2609 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), in brw_urb_WRITE()
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/external/igt-gpu-tools/assembler/ |
D | brw_reg.h | 472 brw_vec1_grf(unsigned nr, unsigned subnr) in brw_vec1_grf() function 729 struct brw_reg reg = brw_vec1_grf(0, 0); in brw_vec1_indirect()
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D | brw_eu_emit.c | 2345 retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), in brw_urb_WRITE()
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