| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 1829 auto AndOp = MIRBuilder.buildAnd( in widenScalar()
2431 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); in getBitcastWiderVectorElementOffset()
2569 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); in buildBitFieldInsert()
3178 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); in clampDynamicVectorIndex()
4923 auto MIBTmp = MIRBuilder.buildAnd( in lowerBitCount()
4952 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); in lowerBitCount()
4961 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); in lowerBitCount()
4962 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); in lowerBitCount()
4975 auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0); in lowerBitCount()
5029 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); in lowerU64ToF32BitOps()
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| D | IRTranslator.cpp | 1072 auto AndOp = MIB.buildAnd(SwitchTy, SwitchVal, CstMask); in emitBitTestCase()
2512 auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst); in translateAlloca()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3872 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); in lowerU64ToF32BitOps()
3875 auto T = MIRBuilder.buildAnd(S64, U, Mask1); in lowerU64ToF32BitOps()
3886 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); in lowerU64ToF32BitOps()
4062 auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask); in lowerFCopySign()
4066 auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask); in lowerFCopySign()
4072 auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask); in lowerFCopySign()
4078 auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask); in lowerFCopySign()
4155 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); in lowerIntrinsicRound()
4276 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); in lowerDynStackAlloc()
4348 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); in lowerInsert()
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| D | IRTranslator.cpp | 1852 auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst); in translateAlloca()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1404 auto And = B.buildAnd(S1, Lt0, NeTrunc); in legalizeFceil()
1452 auto SignBit = B.buildAnd(S32, Hi, SignBitMask); in legalizeIntrinsicTrunc()
1463 auto Tmp0 = B.buildAnd(S64, Src, Not); in legalizeIntrinsicTrunc()
1866 B.buildAnd(DstReg, AndMaskSrc, B.buildConstant(S32, Mask >> Shift)); in loadInputValue()
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| D | AMDGPURegisterBankInfo.cpp | 1921 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0); in applyMappingImpl()
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| /external/llvm-project/llvm/unittests/CodeGen/GlobalISel/ |
| D | LegalizerHelperTest.cpp | 656 auto And = B.buildAnd(V5S32, Op0, Op1); in TEST_F()
710 auto And = B.buildAnd(v2s32, Val0, Val1); in TEST_F()
790 B.buildAnd(PhiTy, Phi.getReg(0), Phi.getReg(0)); in TEST_F()
2697 auto And = B.buildAnd(V4S8, Val0, Val1); in TEST_F()
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| D | PatternMatchTest.cpp | 115 auto MIBAnd = B.buildAnd(s64, Copies[0], Copies[1]); in TEST_F()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 118 Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), in tryCombineZExt()
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| D | MachineIRBuilder.h | 1312 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, in buildAnd() function
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 124 Builder.buildAnd(DstReg, Extended, Mask); in tryCombineZExt()
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| D | MachineIRBuilder.h | 1483 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, in buildAnd() function
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1908 auto And = B.buildAnd(S1, Lt0, NeTrunc); in legalizeFceil()
1972 auto SignBit = B.buildAnd(S32, Hi, SignBitMask); in legalizeIntrinsicTrunc()
1983 auto Tmp0 = B.buildAnd(S64, Src, Not); in legalizeIntrinsicTrunc()
2716 B.buildAnd(DstReg, AndMaskSrc, B.buildConstant(S32, Mask >> Shift)); in loadInputValue()
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| D | AMDGPURegisterBankInfo.cpp | 1565 auto ClampOffset = B.buildAnd(S32, OffsetReg, OffsetMask); in applyMappingBFEIntrinsic()
1632 auto ExtLo = B.buildAnd(S32, Bitcast, B.buildConstant(S32, 0xffff)); in unpackV2S16ToS32()
2672 ZextLo = B.buildAnd(S32, Lo, MaskLo).getReg(0); in applyMappingImpl()
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