| /external/llvm-project/llvm/unittests/CodeGen/GlobalISel/ |
| D | LegalizerHelperTest.cpp | 1373 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
1430 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
1488 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
1540 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
1592 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
1644 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
1696 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
1748 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
1795 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
1842 auto MIBExt = B.buildAnyExt(S128, Copies[0]); in TEST_F()
[all …]
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| D | PatternMatchTest.cpp | 271 auto MIBAExt = B.buildAnyExt(s64, MIBTrunc); in TEST_F()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsLegalizerInfo.cpp | 373 Val = MIRBuilder.buildAnyExt(s32, Val).getReg(0); in legalizeCustom()
375 Val = MIRBuilder.buildAnyExt(s64, Val).getReg(0); in legalizeCustom()
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| D | MipsCallLowering.cpp | 301 return MIRBuilder.buildAnyExt(LocTy, ValReg).getReg(0); in extendRegister()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 58 ExtReg = MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in assignValueToReg()
237 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i)); in unpackRegsToOrigType()
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| D | AMDGPULegalizerInfo.cpp | 2308 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0)); in handleD16VData()
2330 Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0); in legalizeRawBufferStore()
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| D | AMDGPURegisterBankInfo.cpp | 1853 auto Ext = B.buildAnyExt(DstTy, SrcReg); in applyMappingImpl()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPostLegalizerCombiner.cpp | 240 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN()
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| D | AMDGPUCallLowering.cpp | 48 return MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0); in extendRegisterMin32()
376 B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i)); in unpackRegsToOrigType()
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| D | AMDGPULegalizerInfo.cpp | 3542 WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0)); in handleD16VData()
3593 Register AnyExt = B.buildAnyExt(LLT::scalar(32), VData).getReg(0); in fixStoreSourceType()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 141 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg); in assignValueToReg()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 140 MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg).getReg(0); in assignValueToReg()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 532 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
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| D | InlineAsmLowering.cpp | 266 Src = MIRBuilder.buildAnyExt(LLT::scalar(DstSize), Src).getReg(0); in buildAnyextOrCopy()
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| D | LegalizerHelper.cpp | 792 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); in narrowScalar()
950 MIRBuilder.buildAnyExt(DstReg, TmpReg); in narrowScalar()
1574 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); in widenScalarUnmergeValues()
1603 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); in widenScalarUnmergeValues()
1709 Src = MIRBuilder.buildAnyExt(WideTy, Src); in widenScalarExtract()
1782 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); in widenScalarAddSubShlSat()
1784 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); in widenScalarAddSubShlSat()
2757 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); in lowerStore()
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| D | MachineIRBuilder.cpp | 404 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res, in buildAnyExt() function in MachineIRBuilder
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 471 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
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| D | MachineIRBuilder.cpp | 409 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res, in buildAnyExt() function in MachineIRBuilder
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| D | LegalizerHelper.cpp | 804 MIRBuilder.buildAnyExt(DstReg, TmpReg); in narrowScalar()
1378 Src = MIRBuilder.buildAnyExt(WideTy, Src); in widenScalarExtract()
2179 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); in lower()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 337 MIRBuilder.buildAnyExt(ExtReg, ValReg); in extendRegister()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 505 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 180 ValVReg = MIRBuilder.buildAnyExt(LLT::scalar(Size * 8), ValVReg) in assignValueToAddress()
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 597 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
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