| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 539 B.buildBuildVector(OrigRegs[0], Regs); in packSplitRegsToOrigType()
556 B.buildBuildVector(OrigRegs[0], EltMerges); in packSplitRegsToOrigType()
560 auto BV = B.buildBuildVector(BVType, Regs); in packSplitRegsToOrigType()
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| D | AMDGPULegalizerInfo.cpp | 1794 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0); in legalizeAtomicCmpXChg()
2312 return B.buildBuildVector(LLT::vector(NumElts, S32), WideRegs).getReg(0); in handleD16VData()
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| D | AMDGPURegisterBankInfo.cpp | 979 auto Merge = B.buildBuildVector(OpTy, ReadlanePieces); in executeInWaterfallLoop()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 211 MIRBuilder.buildBuildVector(DstReg, PartRegs); in insertParts()
622 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
748 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
2347 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorImplicitDef()
2440 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorBasic()
2585 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorCasts()
2652 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorCmp()
2724 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorSelect()
2880 auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector); in fewerElementsVectorBuildVector()
3554 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalarExtract()
[all …]
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| D | IRTranslator.cpp | 2163 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
2173 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
2190 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
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| D | CombinerHelper.cpp | 187 Builder.buildBuildVector(NewDstReg, Ops); in applyCombineConcatVectors()
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| D | MachineIRBuilder.cpp | 611 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res, in buildBuildVector() function in MachineIRBuilder
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 751 B.buildBuildVector(OrigRegs[0], Regs); in packSplitRegsToOrigType()
768 B.buildBuildVector(OrigRegs[0], EltMerges); in packSplitRegsToOrigType()
772 auto BV = B.buildBuildVector(BVType, Regs); in packSplitRegsToOrigType()
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| D | AMDGPULegalizerInfo.cpp | 2479 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0); in legalizeAtomicCmpXChg()
3546 return B.buildBuildVector(LLT::vector(NumElts, S32), WideRegs).getReg(0); in handleD16VData()
3555 return B.buildBuildVector(LLT::vector(2, S32), PackedRegs).getReg(0); in handleD16VData()
3564 Reg = B.buildBuildVector(LLT::vector(6, S16), PackedRegs).getReg(0); in handleD16VData()
3575 return B.buildBuildVector(LLT::vector(4, S32), PackedRegs).getReg(0); in handleD16VData()
3985 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImageA16AddressToDwords()
3989 B.buildBuildVector( in packImageA16AddressToDwords()
4024 auto VAddr = B.buildBuildVector(LLT::vector(NumAddrRegs, 32), AddrRegs); in convertImageAddrToPacked()
4121 auto Concat = B.buildBuildVector(PackedTy, {VData0, VData1}); in legalizeImageIntrinsic()
4401 B.buildBuildVector(DstReg, ResultRegs); in legalizeImageIntrinsic()
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| D | AMDGPURegisterBankInfo.cpp | 1000 auto Merge = B.buildBuildVector(OpTy, ReadlanePieces); in executeInWaterfallLoop()
2093 B.buildBuildVector(MI.getOperand(0), Ops); in foldInsertEltToCmpSelect()
2095 auto Vec = B.buildBuildVector(MergeTy, Ops); in foldInsertEltToCmpSelect()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 217 MIRBuilder.buildBuildVector(DstReg, PartRegs); in insertParts()
805 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
895 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
2493 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); in bitcastExtractVectorElt()
3357 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorCasts()
3424 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorCmp()
3496 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorSelect()
4540 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalarExtract()
4617 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalarInsert()
5741 MIRBuilder.buildBuildVector(DstReg, BuildVec); in lowerShuffleVector()
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| D | IRTranslator.cpp | 2817 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
2828 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
2845 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
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| D | MachineIRBuilder.cpp | 613 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res, in buildBuildVector() function in MachineIRBuilder
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| D | CombinerHelper.cpp | 172 Builder.buildBuildVector(NewDstReg, Ops); in applyCombineConcatVectors()
2682 Builder.buildBuildVector(MI.getOperand(0).getReg(), MatchInfo); in applyCombineInsertVecElts()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 812 MachineInstrBuilder buildBuildVector(const DstOp &Res,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 339 .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)}) in lowerReturn()
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64CallLowering.cpp | 356 .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)}) in lowerReturn()
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 937 MachineInstrBuilder buildBuildVector(const DstOp &Res,
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| /external/llvm-project/llvm/unittests/CodeGen/GlobalISel/ |
| D | LegalizerHelperTest.cpp | 968 auto BV0 = B.buildBuildVector(V2S16, {Constant0, Constant1}); in TEST_F()
969 auto BV1 = B.buildBuildVector(V2S16, {Constant0, Constant1}); in TEST_F()
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