| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVCallLowering.cpp | 28 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET); in lowerReturn()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVCallLowering.cpp | 28 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET); in lowerReturn()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegBankSelect.cpp | 164 MI = MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY) in repairReg()
194 MIRBuilder.buildInstrNoInsert(MergeOp) in repairReg()
203 MIRBuilder.buildInstrNoInsert(TargetOpcode::G_UNMERGE_VALUES); in repairReg()
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| D | MachineIRBuilder.cpp | 75 return insertInstr(buildInstrNoInsert(Opcode)); in buildInstr()
78 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) { in buildInstrNoInsert() function in MachineIRBuilder
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| D | LegalizerHelper.cpp | 2502 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) in fewerElementsVectorMultiEltType()
2510 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) in fewerElementsVectorMultiEltType()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | RegBankSelect.cpp | 164 MI = MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY) in repairReg()
194 MIRBuilder.buildInstrNoInsert(MergeOp) in repairReg()
203 MIRBuilder.buildInstrNoInsert(TargetOpcode::G_UNMERGE_VALUES); in repairReg()
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| D | InlineAsmLowering.cpp | 354 auto Inst = MIRBuilder.buildInstrNoInsert(TargetOpcode::INLINEASM) in lowerInlineAsm()
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| D | MachineIRBuilder.cpp | 40 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) { in buildInstrNoInsert() function in MachineIRBuilder
100 auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE); in buildConstDbgValue()
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| D | IRTranslator.cpp | 2154 MIRBuilder.buildInstrNoInsert(TargetOpcode::LOCAL_ESCAPE) in translateKnownIntrinsic()
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| D | LegalizerHelper.cpp | 3275 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) in fewerElementsVectorMultiEltType()
3283 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) in fewerElementsVectorMultiEltType()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 192 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); in lowerReturn()
403 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc) in lowerCall()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 192 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); in lowerReturn()
400 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc) in lowerCall()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 272 auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL)); in lowerReturn()
520 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); in lowerCall()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CallLowering.cpp | 260 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR); in lowerReturn()
809 auto MIB = MIRBuilder.buildInstrNoInsert(Opc); in lowerTailCall()
970 auto MIB = MIRBuilder.buildInstrNoInsert(Opc); in lowerCall()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 272 auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL)); in lowerReturn()
523 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); in lowerCall()
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64CallLowering.cpp | 278 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR); in lowerReturn()
834 auto MIB = MIRBuilder.buildInstrNoInsert(Opc); in lowerTailCall()
994 auto MIB = MIRBuilder.buildInstrNoInsert(Opc); in lowerCall()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 380 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA); in lowerReturn()
531 MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert( in lowerCall()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 417 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA); in lowerReturn()
569 MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert( in lowerCall()
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 371 return insertInstr(buildInstrNoInsert(Opcode)); in buildInstr()
379 MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 476 auto Ret = B.buildInstrNoInsert(ReturnOpc); in lowerReturn()
1198 auto MIB = MIRBuilder.buildInstrNoInsert(Opc); in lowerCall()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 317 auto Ret = B.buildInstrNoInsert(ReturnOpc); in lowerReturn()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 340 MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
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