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Searched refs:buildMerge (Results 1 – 25 of 29) sorted by relevance

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/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DMachineIRBuilderTest.cpp200 auto Merge = B.buildMerge(S128, {Copies[0], Copies[1]}); in TEST_F()
340 B.buildMerge(LLT::scalar(128), {RegC0, RegC1, RegC2, RegC3}); in TEST_F()
344 B.buildMerge(V2x32, {RegC0, RegC1}).getReg(0); in TEST_F()
346 B.buildMerge(V2x32, {RegC2, RegC3}).getReg(0); in TEST_F()
348 B.buildMerge(LLT::vector(4, 32), {RegC0C1, RegC2C3}); in TEST_F()
DLegalizerHelperTest.cpp1023 auto Merge0 = B.buildMerge(S24, Merge0Ops); in TEST_F()
1032 auto Merge1 = B.buildMerge(S21, Merge1Ops); in TEST_F()
1038 auto Merge2 = B.buildMerge(S16, Merge2Ops); in TEST_F()
1112 auto Merge = B.buildMerge(P0, {Lo, Hi}); in TEST_F()
1312 auto MIBMerge = B.buildMerge(S128, {Copies[1], Copies[2]}); in TEST_F()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsLegalizerInfo.cpp413 MIRBuilder.buildMerge(Val, {Load_P2Half, Load_Rem}); in legalizeCustom()
415 auto Merge = MIRBuilder.buildMerge(s64, {Load_P2Half, Load_Rem}); in legalizeCustom()
442 auto Bitcast = MIRBuilder.buildMerge(s64, {Src, C_HiMask.getReg(0)}); in legalizeCustom()
DMipsCallLowering.cpp148 MIRBuilder.buildMerge(ValVReg, {Lo, Hi}); in assignValueToReg()
208 MIRBuilder.buildMerge(ArgsReg, VRegs); in handleSplit()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp204 MIRBuilder.buildMerge(DstReg, PartRegs); in insertParts()
624 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
679 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)}); in narrowScalar()
699 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs); in narrowScalar()
750 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
782 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); in narrowScalar()
934 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); in narrowScalar()
1074 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
1094 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs); in narrowScalar()
1280 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); in widenScalarMergeValues()
[all …]
DCallLowering.cpp323 MIRBuilder.buildMerge(Args[i].OrigRegs[0], Args[i].Regs); in handleAssignments()
DMachineIRBuilder.cpp552 buildMerge(Res, Ops); in buildSequence()
572 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge() function in MachineIRBuilder
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp358 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
478 MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs); in lowerCall()
/external/llvm-project/llvm/lib/Target/X86/
DX86CallLowering.cpp355 MIRBuilder.buildMerge(VRegs[Idx][0], Regs); in lowerFormalArguments()
475 MIRBuilder.buildMerge(Info.OrigRet.Regs[0], NewRegs); in lowerCall()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp210 MIRBuilder.buildMerge(DstReg, PartRegs); in insertParts()
360 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); in buildLCMMergePieces()
379 MIRBuilder.buildMerge(DstReg, RemergeRegs); in buildWidenedRemergeToDst()
383 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); in buildWidenedRemergeToDst()
397 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); in buildWidenedRemergeToDst()
807 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
897 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
929 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); in narrowScalar()
1084 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); in narrowScalar()
1218 MIRBuilder.buildMerge(DstReg, DstRegs); in narrowScalar()
[all …]
DMachineIRBuilder.cpp547 buildMerge(Res, Ops); in buildSequence()
567 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge() function in MachineIRBuilder
578 MachineIRBuilder::buildMerge(const DstOp &Res, in buildMerge() function in MachineIRBuilder
DCombinerHelper.cpp271 Builder.buildMerge(NewDstReg, Ops); in applyCombineShuffleVector()
2062 Builder.buildMerge(DstReg, { Narrowed, Zero }); in applyCombineShiftToUnmerge()
2075 Builder.buildMerge(DstReg, { Zero, Narrowed }); in applyCombineShiftToUnmerge()
2085 Builder.buildMerge(DstReg, { Unmerge.getReg(1), Hi }); in applyCombineShiftToUnmerge()
2091 Builder.buildMerge(DstReg, { Hi, Hi }); in applyCombineShiftToUnmerge()
2099 Builder.buildMerge(DstReg, { Lo, Hi }); in applyCombineShiftToUnmerge()
DCallLowering.cpp425 MIRBuilder.buildMerge(Args[i].OrigRegs[0], Args[i].Regs); in handleAssignments()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPULegalizerInfo.cpp1808 B.buildMerge(Dst, {Src, HighAddr}); in legalizeAddrSpaceCast()
1855 auto BuildPtr = B.buildMerge(DstTy, {SrcAsInt, ApertureReg}); in legalizeAddrSpaceCast()
1979 auto SignBit64 = B.buildMerge(S64, {Zero32, SignBit}); in legalizeIntrinsicTrunc()
2055 B.buildMerge(Dst, { Lo, Hi }); in legalizeFPTOI()
2635 auto Merge = B.buildMerge(S32, {Src0, Src1}); in legalizeBuildVector()
2879 auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi}); in legalizeUDIV_UREM64Impl()
2894 auto Add1 = B.buildMerge(S64, {Add1_Lo, Add1_Hi}); in legalizeUDIV_UREM64Impl()
2907 auto Add2 = B.buildMerge(S64, {Add2_Lo, Add2_Hi}); in legalizeUDIV_UREM64Impl()
2921 auto Sub1 = B.buildMerge(S64, {Sub1_Lo, Sub1_Hi}); in legalizeUDIV_UREM64Impl()
2944 auto Sub2 = B.buildMerge(S64, {Sub2_Lo, Sub2_Hi}); in legalizeUDIV_UREM64Impl()
[all …]
DAMDGPUCallLowering.cpp403 UnmergeSrc = B.buildMerge(LCMTy, MergeParts).getReg(0); in unpackRegsToOrigType()
717 B.buildMerge(OrigRegs[0], Regs); in packSplitRegsToOrigType()
719 auto Widened = B.buildMerge(LLT::scalar(SrcSize), Regs); in packSplitRegsToOrigType()
761 auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt)); in packSplitRegsToOrigType()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp495 B.buildMerge(OrigRegs[0], Regs); in packSplitRegsToOrigType()
549 auto Merge = B.buildMerge(RealDstEltTy, Regs.take_front(PartsPerElt)); in packSplitRegsToOrigType()
DAMDGPULegalizerInfo.cpp1295 B.buildMerge(Dst, {Src, HighAddr.getReg(0)}); in legalizeAddrSpaceCast()
1349 B.buildMerge(BuildPtr, {SrcAsInt, ApertureReg}); in legalizeAddrSpaceCast()
1459 auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)}); in legalizeIntrinsicTrunc()
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h274 Builder.buildMerge(DstReg, SrcRegs); in tryCombineTrunc()
675 Builder.buildMerge(DefReg, Regs); in tryCombineUnmergeValues()
DMachineIRBuilder.h908 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
909 MachineInstrBuilder buildMerge(const DstOp &Res,
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallLowering.cpp389 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs); in assignCustomValue()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DLegalizationArtifactCombiner.h370 Builder.buildMerge(DefReg, Regs); in tryCombineMerges()
DMachineIRBuilder.h785 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp392 MIRBuilder.buildMerge(Arg.Regs[0], NewRegs); in assignCustomValue()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp220 MIRBuilder.buildMerge(ArgsReg, VRegs); in handleSplit()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp325 MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef.getReg(0)}) in lowerReturn()

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