Searched refs:buildMul (Results 1 – 12 of 12) sorted by relevance
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUAtomicOptimizer.cpp | 407 static Value *buildMul(IRBuilder<> &B, Value *LHS, Value *RHS) { in buildMul() function
531 NewV = buildMul(B, V, Ctpop); in optimizeAtomic()
551 NewV = buildMul(B, V, B.CreateAnd(Ctpop, 1)); in optimizeAtomic()
630 LaneOffset = buildMul(B, V, Mbcnt); in optimizeAtomic()
641 LaneOffset = buildMul(B, V, B.CreateAnd(Mbcnt, 1)); in optimizeAtomic()
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| D | AMDGPULegalizerInfo.cpp | 2790 auto NegYZ = B.buildMul(S32, NegY, Z); in legalizeUDIV_UREM32Impl()
2795 auto R = B.buildSub(S32, X, B.buildMul(S32, Q, Y)); in legalizeUDIV_UREM32Impl()
2884 auto MulLo1 = B.buildMul(S64, NegDenom, Rcp); in legalizeUDIV_UREM64Impl()
2896 auto MulLo2 = B.buildMul(S64, NegDenom, Add1); in legalizeUDIV_UREM64Impl()
2914 auto Mul3 = B.buildMul(S64, Denom, MulHi3); in legalizeUDIV_UREM64Impl()
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| /external/llvm-project/llvm/unittests/CodeGen/GlobalISel/ |
| D | PatternMatchTest.cpp | 63 auto MIBMul = B.buildMul(s64, MIBAdd, Copies[2]); in TEST_F()
81 auto MIBMul2 = B.buildMul(s64, Copies[0], B.buildConstant(s64, 42)); in TEST_F()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 1259 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 2484 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); in bitcastExtractVectorElt()
2864 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); in lower()
3197 auto Mul = MIRBuilder.buildMul(IdxTy, Index, in getVectorElementPointer()
4394 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); in multiplyRegisters()
4405 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); in multiplyRegisters()
4981 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); in lowerBitCount()
6197 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); in lowerSMULH_UMULH()
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| D | IRTranslator.cpp | 1528 MIRBuilder.buildMul(OffsetTy, IdxReg, ElementSizeMIB).getReg(0); in translateGetElementPtr()
2501 MIRBuilder.buildMul(AllocSize, NumElts, TySize); in translateAlloca()
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| D | CombinerHelper.cpp | 1050 Val = MIB.buildMul(ExtType, ZExt, MagicMI).getReg(0); in getMemsetValue()
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 1406 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 956 Val = MIB.buildMul(ExtType, ZExt, MagicMI).getReg(0); in getMemsetValue()
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| D | LegalizerHelper.cpp | 1955 MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg()); in lower()
1973 MIRBuilder.buildMul(Res, LHS, RHS); in lower()
3408 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); in multiplyRegisters()
3419 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); in multiplyRegisters()
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| D | IRTranslator.cpp | 1104 MIRBuilder.buildMul(OffsetTy, ElementSizeMIB, IdxReg).getReg(0); in translateGetElementPtr()
1837 MIRBuilder.buildMul(AllocSize, NumElts, TySize); in translateAlloca()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 2167 auto Mul = B.buildMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64()
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