| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 1063 Ptr = MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); in optimizeMemset()
1168 LoadPtr = MIB.buildPtrAdd(PtrTy, Src, Offset).getReg(0); in optimizeMemcpy()
1174 CurrOffset == 0 ? Dst : MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); in optimizeMemcpy()
1265 LoadPtr = MIB.buildPtrAdd(PtrTy, Src, Offset).getReg(0); in optimizeMemmove()
1282 StorePtr = MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); in optimizeMemmove()
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| D | MachineIRBuilder.cpp | 214 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res, in buildPtrAdd() function in MachineIRBuilder
237 return buildPtrAdd(Res, Op0, Cst.getReg(0)); in materializePtrAdd()
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| D | IRTranslator.cpp | 1088 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0)) in translateGetElementPtr()
1108 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0); in translateGetElementPtr()
1115 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0)); in translateGetElementPtr()
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| D | LegalizerHelper.cpp | 2120 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); in lower()
2193 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); in lower()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsLegalizerInfo.cpp | 378 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); in legalizeCustom()
407 auto Addr = MIRBuilder.buildPtrAdd(PtrTy, BaseAddr, C_P2HalfMemSize); in legalizeCustom()
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| D | MipsCallLowering.cpp | 270 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64LegalizerInfo.cpp | 747 auto ListTmp = MIRBuilder.buildPtrAdd(PtrTy, List, AlignMinus1.getReg(0)); in legalizeVaArg()
762 auto NewList = MIRBuilder.buildPtrAdd(PtrTy, DstPtr, Size.getReg(0)); in legalizeVaArg()
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| D | AArch64CallLowering.cpp | 163 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 182 MachineInstrBuilder MachineIRBuilder::buildPtrAdd(const DstOp &Res, in buildPtrAdd() function in MachineIRBuilder
205 return buildPtrAdd(Res, Op0, Cst.getReg(0)); in materializePtrAdd()
372 auto Ptr = buildPtrAdd(PtrTy, BasePtr, ConstOffset); in buildLoadFromOffset()
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| D | CombinerHelper.cpp | 1161 Ptr = MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); in optimizeMemset()
1263 LoadPtr = MIB.buildPtrAdd(PtrTy, Src, Offset).getReg(0); in optimizeMemcpy()
1269 CurrOffset == 0 ? Dst : MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); in optimizeMemcpy()
1358 LoadPtr = MIB.buildPtrAdd(PtrTy, Src, Offset).getReg(0); in optimizeMemmove()
1375 StorePtr = MIB.buildPtrAdd(PtrTy, Dst, Offset).getReg(0); in optimizeMemmove()
2190 auto PtrAdd = Builder.buildPtrAdd(PtrTy, LHS, RHS); in applyCombineAddP2IToPtrAdd()
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| D | IRTranslator.cpp | 1505 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, OffsetMIB.getReg(0)) in translateGetElementPtr()
1532 BaseReg = MIRBuilder.buildPtrAdd(PtrTy, BaseReg, GepOffsetReg).getReg(0); in translateGetElementPtr()
1539 MIRBuilder.buildPtrAdd(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0)); in translateGetElementPtr()
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| D | LegalizerHelper.cpp | 2694 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); in lowerLoad()
2771 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); in lowerStore()
3201 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); in getVectorElementPointer()
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64LegalizerInfo.cpp | 908 auto ListTmp = MIRBuilder.buildPtrAdd(PtrTy, List, AlignMinus1.getReg(0)); in legalizeVaArg()
921 auto NewList = MIRBuilder.buildPtrAdd(PtrTy, DstPtr, Size.getReg(0)); in legalizeVaArg()
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| D | AArch64CallLowering.cpp | 160 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 118 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86CallLowering.cpp | 115 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 105 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMCallLowering.cpp | 109 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 226 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); in getStackAddress()
511 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
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| D | AMDGPURegisterBankInfo.cpp | 1276 auto PtrAdd = B.buildPtrAdd(PtrTy, SPCopy, ScaledSize); in applyMappingDynStackAlloc()
1280 B.buildPtrAdd(Dst, SPCopy, ScaledSize); in applyMappingDynStackAlloc()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 359 B.buildPtrAdd(DstReg, KernArgSegmentVReg, OffsetReg); in lowerParameterPtr()
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| D | AMDGPULegalizerInfo.cpp | 2275 B.buildPtrAdd(DstReg, KernargPtrReg, B.buildConstant(IdxTy, Offset).getReg(0)); in legalizeImplicitArgPtr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 302 MIRBuilder.buildPtrAdd(AddrReg, SPReg, OffsetReg); in getStackAddress()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 419 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 458 MachineInstrBuilder buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
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