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Searched refs:buildSelect (Results 1 – 12 of 12) sorted by relevance

/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp1130 MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH); in narrowScalar()
3035 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); in lower()
3488 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, in fewerElementsVectorSelect()
4223 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); in narrowScalarShift()
4224 auto Hi = MIRBuilder.buildSelect( in narrowScalarShift()
4225 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); in narrowScalarShift()
4251 auto Lo = MIRBuilder.buildSelect( in narrowScalarShift()
4252 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); in narrowScalarShift()
4254 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); in narrowScalarShift()
4715 auto Select = MIRBuilder.buildSelect(NarrowTy, in narrowScalarSelect()
[all …]
DMachineIRBuilder.cpp743 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res, in buildSelect() function in MachineIRBuilder
DIRTranslator.cpp1419 MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i], Flags); in translateSelect()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp980 MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH); in narrowScalar()
2270 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); in lower()
2716 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, in fewerElementsVectorSelect()
3237 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); in narrowScalarShift()
3238 auto Hi = MIRBuilder.buildSelect( in narrowScalarShift()
3239 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); in narrowScalarShift()
3265 auto Lo = MIRBuilder.buildSelect( in narrowScalarShift()
3266 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); in narrowScalarShift()
3268 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); in narrowScalarShift()
3705 auto Select = MIRBuilder.buildSelect(NarrowTy, in narrowScalarSelect()
[all …]
DMachineIRBuilder.cpp714 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res, in buildSelect() function in MachineIRBuilder
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPULegalizerInfo.cpp1826 B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0)); in legalizeAddrSpaceCast()
1856 B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull); in legalizeAddrSpaceCast()
1883 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFrint()
1909 auto Add = B.buildSelect(S64, And, One, Zero); in legalizeFceil()
1989 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc()
1990 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1); in legalizeIntrinsicTrunc()
2613 CorrectedFract = B.buildSelect(S64, IsNan, ModSrc, Min, Flags).getReg(0); in legalizeFFloor()
2801 Q = B.buildSelect(S32, Cond, B.buildAdd(S32, Q, One), Q); in legalizeUDIV_UREM32Impl()
2802 R = B.buildSelect(S32, Cond, B.buildSub(S32, R, Y), R); in legalizeUDIV_UREM32Impl()
2807 B.buildSelect(DstReg, Cond, B.buildAdd(S32, Q, One), Q); in legalizeUDIV_UREM32Impl()
[all …]
DAMDGPURegisterBankInfo.cpp140 B.buildSelect(DstReg, SrcReg, True, False); in applyBank()
1646 return B.buildSelect(Dst, Cmp, Src0, Src1); in buildExpandedScalarMinMax()
1996 auto S = B.buildSelect(EltTy, Cmp, in foldExtractEltToCmpSelect()
2081 auto S = B.buildSelect(EltTy, Cmp, InsRegs[L], in foldInsertEltToCmpSelect()
2256 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]); in applyMappingImpl()
2257 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]); in applyMappingImpl()
2604 B.buildSelect(DefRegs[0], SrcReg, True, False); in applyMappingImpl()
2607 auto Sel = B.buildSelect(SelType, SrcReg, True, False); in applyMappingImpl()
2611 B.buildSelect(DstReg, SrcReg, True, False); in applyMappingImpl()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPULegalizerInfo.cpp1315 B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0)); in legalizeAddrSpaceCast()
1350 B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0)); in legalizeAddrSpaceCast()
1379 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2); in legalizeFrint()
1405 auto Add = B.buildSelect(S64, And, One, Zero); in legalizeFceil()
1469 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc()
1470 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1); in legalizeIntrinsicTrunc()
2230 auto Sel = B.buildSelect(S32, CmpRes, C1, C2, Flags); in legalizeFDIVFastIntrin()
DAMDGPURegisterBankInfo.cpp81 B.buildSelect(DstReg, SrcReg, True, False); in applyBank()
1240 B.buildSelect(Dst, Cmp, Src0, Src1); in lowerScalarMinMax()
1612 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]); in applyMappingImpl()
1613 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]); in applyMappingImpl()
1836 B.buildSelect(DefRegs[0], SrcReg, True, False); in applyMappingImpl()
1839 auto Sel = B.buildSelect(SelType, SrcReg, True, False); in applyMappingImpl()
1843 B.buildSelect(DstReg, SrcReg, True, False); in applyMappingImpl()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h935 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h1077 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DLegalizerHelperTest.cpp2653 auto Select = B.buildSelect(V4S8, Cond, Val0, Val1); in TEST_F()
2676 auto VSelect = B.buildSelect(V4S8, VCond, Val0, Val1); in TEST_F()