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Searched refs:buildUndef (Results 1 – 23 of 23) sorted by relevance

/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DCSETest.cpp78 auto Undef0 = CSEB.buildUndef(s32); in TEST_F()
79 auto Undef1 = CSEB.buildUndef(s32); in TEST_F()
136 auto Undef0 = CSEB.buildUndef(s16); in TEST_F()
137 auto Undef1 = CSEB.buildUndef(s16); in TEST_F()
DLegalizerHelperTest.cpp654 auto Op0 = B.buildUndef(V5S32); in TEST_F()
655 auto Op1 = B.buildUndef(V5S32); in TEST_F()
759 auto InitVal = B.buildUndef(PhiTy); in TEST_F()
768 auto MidVal = B.buildUndef(PhiTy); in TEST_F()
2578 auto Ptr = B.buildUndef(P0); in TEST_F()
2612 auto Ptr = B.buildUndef(P0); in TEST_F()
2618 auto Val = B.buildUndef(V4S8); in TEST_F()
2649 auto Cond = B.buildUndef(S1); in TEST_F()
2675 auto VCond = B.buildUndef(LLT::vector(4, 1)); in TEST_F()
2778 auto Implicit1 = B.buildUndef(S64); in TEST_F()
[all …]
DMachineIRBuilderTest.cpp312 auto Ptr = B.buildUndef(P0); in TEST_F()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DCombinerHelper.cpp152 Undef = Builder.buildUndef(OpType.getScalarType()); in matchCombineConcatVectors()
185 Builder.buildUndef(NewDstReg); in applyCombineConcatVectors()
266 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
DLegalizerHelper.cpp219 MIRBuilder.buildUndef(CurResultReg); in insertParts()
618 MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg()); in narrowScalar()
1160 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); in moreElementsVectorSrc()
1170 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); in moreElementsVectorSrc()
1270 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()
2340 MIRBuilder.buildUndef(TmpReg); in fewerElementsVectorImplicitDef()
2375 MIRBuilder.buildUndef(AccumDstReg); in fewerElementsVectorBasic()
2856 UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0); in fewerElementsVectorBuildVector()
4215 Val = MIRBuilder.buildUndef(DstTy).getReg(0); in lowerShuffleVector()
4230 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); in lowerShuffleVector()
DCallLowering.cpp145 MIRBuilder.buildUndef(Dst); in packRegs()
DMachineIRBuilder.cpp557 buildUndef(ResIn); in buildSequence()
568 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { in buildUndef() function in MachineIRBuilder
DIRTranslator.cpp1519 MIRBuilder.buildUndef(Undef); in translateKnownIntrinsic()
1773 MIRBuilder.buildUndef(Undef); in translateLandingPad()
2141 EntryBuilder->buildUndef(Reg); in translate()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp249 auto ImpDef = B.buildUndef(BigTy); in unpackRegsToOrigType()
639 B.buildUndef(VRegs[Idx][I]); in lowerFormalArguments()
DAMDGPULegalizerInfo.cpp1553 B.buildUndef(Dst); in legalizeExtractVectorElt()
1583 B.buildUndef(Dst); in legalizeInsertVectorElt()
DAMDGPURegisterBankInfo.cpp763 Register InitReg = B.buildUndef(ResTy).getReg(0); in executeInWaterfallLoop()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp323 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
336 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp398 Register Undef = B.buildUndef(SrcTy).getReg(0); in unpackRegsToOrigType()
682 Register Undef = B.buildUndef(PartLLT).getReg(0); in mergeVectorRegsToResultRegs()
851 B.buildUndef(VRegs[Idx][I]); in lowerFormalArguments()
DAMDGPULegalizerInfo.cpp2105 B.buildUndef(Dst); in legalizeExtractVectorElt()
2137 B.buildUndef(Dst); in legalizeInsertVectorElt()
2276 B.buildUndef(DstReg); in legalizeGlobalValue()
3554 PackedRegs.resize(2, B.buildUndef(S32).getReg(0)); in handleD16VData()
3563 PackedRegs.resize(6, B.buildUndef(S16).getReg(0)); in handleD16VData()
3574 PackedRegs.resize(4, B.buildUndef(S32).getReg(0)); in handleD16VData()
3985 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImageA16AddressToDwords()
4019 auto Undef = B.buildUndef(S32); in convertImageAddrToPacked()
4086 B.buildUndef(MI.getOperand(0)); in legalizeImageIntrinsic()
4392 Register Undef = B.buildUndef(Ty).getReg(0); in legalizeImageIntrinsic()
DAMDGPURegisterBankInfo.cpp759 Register InitReg = B.buildUndef(ResTy).getReg(0); in executeInWaterfallLoop()
1185 auto Undef = B.buildUndef(LoadTy); in applyMappingLoad()
1932 B.buildUndef(Hi32Reg); in extendLow32IntoHigh32()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp552 buildUndef(ResIn); in buildSequence()
563 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) { in buildUndef() function in MachineIRBuilder
643 auto UndefVec = buildUndef(DstTy); in buildShuffleSplat()
DLegalizerHelper.cpp225 MIRBuilder.buildUndef(CurResultReg); in insertParts()
297 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in buildLCMMergePieces()
342 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); in buildLCMMergePieces()
791 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); in narrowScalar()
802 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); in narrowScalar()
1355 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); in moreElementsVectorSrc()
1365 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); in moreElementsVectorSrc()
1478 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues()
1523 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); in widenWithUnmerge()
3212 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); in fewerElementsVectorImplicitDef()
[all …]
DCallLowering.cpp183 MIRBuilder.buildUndef(Dst); in packRegs()
DCombinerHelper.cpp137 Undef = Builder.buildUndef(OpType.getScalarType()); in matchCombineConcatVectors()
170 Builder.buildUndef(NewDstReg); in applyCombineConcatVectors()
251 UndefReg = Builder.buildUndef(SrcType).getReg(0); in matchCombineShuffleVector()
2601 Builder.buildUndef(MI.getOperand(0)); in replaceInstWithUndef()
2675 UndefReg = Builder.buildUndef(DstTy.getScalarType()).getReg(0); in applyCombineInsertVecElts()
DIRTranslator.cpp2101 MIRBuilder.buildUndef(Undef); in translateKnownIntrinsic()
2440 MIRBuilder.buildUndef(Undef); in translateLandingPad()
2801 EntryBuilder->buildUndef(Reg); in translate()
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp341 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
353 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h756 MachineInstrBuilder buildUndef(const DstOp &Res);
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h879 MachineInstrBuilder buildUndef(const DstOp &Res);