| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 972 MIRBuilder.buildZExt(DstReg, TmpReg); in narrowScalar()
1407 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); in widenScalarMergeValues()
1415 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); in widenScalarMergeValues()
1783 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) in widenScalarAddSubShlSat()
1819 auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2)); in widenScalar()
1820 auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3)); in widenScalar()
1860 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); in widenScalar()
2557 auto ZextVal = B.buildZExt(TargetTy, InsertReg); in buildBitFieldInsert()
2725 MIRBuilder.buildZExt(DstReg, TmpReg); in lowerLoad()
3001 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); in lower()
[all …]
|
| D | CallLowering.cpp | 542 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
|
| D | MachineIRBuilder.cpp | 414 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res, in buildZExt() function in MachineIRBuilder
|
| D | CombinerHelper.cpp | 1808 Builder.buildZExt(MI.getOperand(0), NarrowShift); in applyCombineShlOfExtend()
1991 Builder.buildZExt(Dst0Reg, ZExtSrcReg); in applyCombineUnmergeZExtToZExt()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 831 MIRBuilder.buildZExt(DstReg, TmpReg); in narrowScalar()
1199 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); in widenScalarMergeValues()
1207 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); in widenScalarMergeValues()
1318 auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg); in widenScalarUnmergeValues()
1484 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); in widenScalar()
2150 MIRBuilder.buildZExt(DstReg, TmpReg); in lower()
2234 MIRBuilder.buildZExt(ZExtCarryIn, CarryIn); in lower()
2266 MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn); in lower()
3440 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); in multiplyRegisters()
3445 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); in multiplyRegisters()
[all …]
|
| D | CallLowering.cpp | 481 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
|
| D | MachineIRBuilder.cpp | 419 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res, in buildZExt() function in MachineIRBuilder
|
| /external/llvm-project/llvm/unittests/CodeGen/GlobalISel/ |
| D | PatternMatchTest.cpp | 272 auto MIBZExt = B.buildZExt(s64, MIBTrunc); in TEST_F()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 1552 B.buildZExt(NewSrcReg, MI.getOperand(4).getReg()); in applyMappingImpl()
1580 B.buildZExt(NewCondReg, CondRegs[0]); in applyMappingImpl()
1632 B.buildZExt(NewCondReg, CondReg); in applyMappingImpl()
1900 ZextLo = B.buildZExt(S32, Lo).getReg(0); in applyMappingImpl()
1903 Register ZextHi = B.buildZExt(S32, Hi).getReg(0); in applyMappingImpl()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 298 return MIRBuilder.buildZExt(LocTy, ValReg).getReg(0); in extendRegister()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64LegalizerInfo.cpp | 679 auto ExtCst = MIRBuilder.buildZExt(LLT::scalar(64), AmtReg); in legalizeShlAshrLshr()
|
| D | AArch64CallLowering.cpp | 296 CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0); in lowerReturn()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 2190 B.buildZExt(NewSrcReg, MI.getOperand(4).getReg()); in applyMappingImpl()
2224 B.buildZExt(NewCondReg, CondRegs[0]); in applyMappingImpl()
2276 B.buildZExt(NewCondReg, CondReg); in applyMappingImpl()
2651 ZextLo = B.buildZExt(S32, Lo).getReg(0); in applyMappingImpl()
2654 Register ZextHi = B.buildZExt(S32, Hi).getReg(0); in applyMappingImpl()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 332 MIRBuilder.buildZExt(ExtReg, ValReg); in extendRegister()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 569 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
|
| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64CallLowering.cpp | 314 CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0); in lowerReturn()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 666 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
|