• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3  * SPDX-License-Identifier: BSD-3-Clause
4  */
5 #ifndef IMX_CLOCK_H
6 #define IMX_CLOCK_H
7 
8 #include <stdint.h>
9 #include <stdbool.h>
10 
11 struct ccm_pll_ctrl {
12 	uint32_t ccm_pll_ctrl;
13 	uint32_t ccm_pll_ctrl_set;
14 	uint32_t ccm_pll_ctrl_clr;
15 	uint32_t ccm_pll_ctrl_tog;
16 };
17 
18 /* Clock gate control */
19 struct ccm_clk_gate_ctrl {
20 	uint32_t ccm_ccgr;
21 	uint32_t ccm_ccgr_set;
22 	uint32_t ccm_ccgr_clr;
23 	uint32_t ccm_ccgr_tog;
24 };
25 
26 #define CCM_CCGR_SETTING0_DOM_CLK_NONE		0
27 #define CCM_CCGR_SETTING0_DOM_CLK_RUN		BIT(0)
28 #define CCM_CCGR_SETTING0_DOM_CLK_RUN_WAIT	BIT(1)
29 #define CCM_CCGR_SETTING0_DOM_CLK_ALWAYS	(BIT(1) | BIT(0))
30 #define CCM_CCGR_SETTING1_DOM_CLK_NONE		0
31 #define CCM_CCGR_SETTING1_DOM_CLK_RUN		BIT(4)
32 #define CCM_CCGR_SETTING1_DOM_CLK_RUN_WAIT	BIT(5)
33 #define CCM_CCGR_SETTING1_DOM_CLK_ALWAYS	(BIT(5) | BIT(4))
34 #define CCM_CCGR_SETTING2_DOM_CLK_NONE		0
35 #define CCM_CCGR_SETTING2_DOM_CLK_RUN		BIT(8)
36 #define CCM_CCGR_SETTING2_DOM_CLK_RUN_WAIT	BIT(9)
37 #define CCM_CCGR_SETTING2_DOM_CLK_ALWAYS	(BIT(9) | BIT(8))
38 #define CCM_CCGR_SETTING3_DOM_CLK_NONE		0
39 #define CCM_CCGR_SETTING3_DOM_CLK_RUN		BIT(12)
40 #define CCM_CCGR_SETTING3_DOM_CLK_RUN_WAIT	BIT(13)
41 #define CCM_CCGR_SETTING3_DOM_CLK_ALWAYS	(BIT(13) | BIT(12))
42 
43 enum {
44 	CCM_CCGR_ID_ADC = 32,
45 	CCM_CCGR_ID_AIPS1TZ = 10,
46 	CCM_CCGR_ID_AIPS2TZ = 11,
47 	CCM_CCGR_ID_AIPS3TZ = 12,
48 	CCM_CCGR_ID_APBHDMA = 20,
49 	CCM_CCGR_ID_CAAM = 36,
50 	CCM_CCGR_ID_CM4 = 1,
51 	CCM_CCGR_ID_CSI = 73,
52 	CCM_CCGR_ID_CSU = 45,
53 	CCM_CCGR_ID_DAP = 47,
54 	CCM_CCGR_ID_DBGMON = 46,
55 	CCM_CCGR_ID_DDRC = 19,
56 	CCM_CCGR_ID_ECSPI1 = 120,
57 	CCM_CCGR_ID_ECSPI2 = 121,
58 	CCM_CCGR_ID_ECSPI3 = 122,
59 	CCM_CCGR_ID_ECSPI4 = 123,
60 	CCM_CCGR_ID_EIM = 22,
61 	CCM_CCGR_ID_ENET1 = 112,
62 	CCM_CCGR_ID_ENET2 = 113,
63 	CCM_CCGR_ID_EPDC = 74,
64 	CCM_CCGR_ID_FLEXCAN1 = 116,
65 	CCM_CCGR_ID_FLEXCAN2 = 117,
66 	CCM_CCGR_ID_FLEXTIMER1 = 128,
67 	CCM_CCGR_ID_FLEXTIMER2 = 129,
68 	CCM_CCGR_ID_GPIO1 = 160,
69 	CCM_CCGR_ID_GPIO2 = 161,
70 	CCM_CCGR_ID_GPIO3 = 162,
71 	CCM_CCGR_ID_GPIO4 = 163,
72 	CCM_CCGR_ID_GPIO5 = 164,
73 	CCM_CCGR_ID_GPIO6 = 165,
74 	CCM_CCGR_ID_GPIO7 = 166,
75 	CCM_CCGR_ID_GPT1 = 124,
76 	CCM_CCGR_ID_GPT2 = 125,
77 	CCM_CCGR_ID_GPT3 = 126,
78 	CCM_CCGR_ID_GPT4 = 127,
79 	CCM_CCGR_ID_I2C1 = 136,
80 	CCM_CCGR_ID_I2C2 = 137,
81 	CCM_CCGR_ID_I2C3 = 138,
82 	CCM_CCGR_ID_I2C4 = 139,
83 	CCM_CCGR_ID_IOMUXC1 = 168,
84 	CCM_CCGR_ID_IOMUXC2 = 169,
85 	CCM_CCGR_ID_KPP = 120,
86 	CCM_CCGR_ID_LCDIF = 75,
87 	CCM_CCGR_ID_MIPI_CSI = 100,
88 	CCM_CCGR_ID_MIPI_DSI = 101,
89 	CCM_CCGR_ID_MIPI_PHY = 102,
90 	CCM_CCGR_ID_MU = 39,
91 	CCM_CCGR_ID_OCOTP = 35,
92 	CCM_CCGR_ID_OCRAM = 17,
93 	CCM_CCGR_ID_OCRAM_S = 18,
94 	CCM_CCGR_ID_PCIE = 96,
95 	CCM_CCGR_ID_PCIE_PHY = 96,
96 	CCM_CCGR_ID_PERFMON1 = 68,
97 	CCM_CCGR_ID_PERFMON2 = 69,
98 	CCM_CCGR_ID_PWM1 = 132,
99 	CCM_CCGR_ID_PWM2 = 133,
100 	CCM_CCGR_ID_PWM3 = 134,
101 	CCM_CCGR_ID_PMM4 = 135,
102 	CCM_CCGR_ID_PXP = 76,
103 	CCM_CCGR_ID_QOS1 = 42,
104 	CCM_CCGR_ID_QOS2 = 43,
105 	CCM_CCGR_ID_QOS3 = 44,
106 	CCM_CCGR_ID_QUADSPI = 21,
107 	CCM_CCGR_ID_RDC = 38,
108 	CCM_CCGR_ID_ROMCP = 16,
109 	CCM_CCGR_ID_SAI1 = 140,
110 	CCM_CCGR_ID_SAI2 = 141,
111 	CCM_CCGR_ID_SAI3 = 142,
112 	CCM_CCGR_ID_SCTR = 34,
113 	CCM_CCGR_ID_SDMA = 72,
114 	CCM_CCGR_ID_SEC = 49,
115 	CCM_CCGR_ID_SEMA42_1 = 64,
116 	CCM_CCGR_ID_SEMA42_2 = 65,
117 	CCM_CCGR_ID_SIM_DISPLAY = 5,
118 	CCM_CCGR_ID_SIM_ENET = 6,
119 	CCM_CCGR_ID_SIM_M = 7,
120 	CCM_CCGR_ID_SIM_MAIN = 4,
121 	CCM_CCGR_ID_SIM_S = 8,
122 	CCM_CCGR_ID_SIM_WAKEUP = 9,
123 	CCM_CCGR_ID_SIM1 = 144,
124 	CCM_CCGR_ID_SIM2 = 145,
125 	CCM_CCGR_ID_SIM_NAND = 20,
126 	CCM_CCGR_ID_DISPLAY_CM4 = 1,
127 	CCM_CCGR_ID_DRAM = 19,
128 	CCM_CCGR_ID_SNVS = 37,
129 	CCM_CCGR_ID_SPBA = 12,
130 	CCM_CCGR_ID_TRACE = 48,
131 	CCM_CCGR_ID_TZASC = 19,
132 	CCM_CCGR_ID_UART1 = 148,
133 	CCM_CCGR_ID_UART2 = 149,
134 	CCM_CCGR_ID_UART3 = 150,
135 	CCM_CCGR_ID_UART4 = 151,
136 	CCM_CCGR_ID_UART5 = 152,
137 	CCM_CCGR_ID_UART6 = 153,
138 	CCM_CCGR_ID_UART7 = 154,
139 	CCM_CCGR_ID_USB_HS = 40,
140 	CCM_CCGR_ID_USB_IPG = 104,
141 	CCM_CCGR_ID_USB_PHY_480MCLK = 105,
142 	CCM_CCGR_ID_USB_OTG1_PHY = 106,
143 	CCM_CCGR_ID_USB_OTG2_PHY = 107,
144 	CCM_CCGR_ID_USBHDC1 = 108,
145 	CCM_CCGR_ID_USBHDC2 = 109,
146 	CCM_CCGR_ID_USBHDC3 = 110,
147 	CCM_CCGR_ID_WDOG1 = 156,
148 	CCM_CCGR_ID_WDOG2 = 157,
149 	CCM_CCGR_ID_WDOG3 = 158,
150 	CCM_CCGR_ID_WDOG4 = 159,
151 };
152 
153 /* Clock target block */
154 struct ccm_target_root_ctrl {
155 	uint32_t ccm_target_root;
156 	uint32_t ccm_target_root_set;
157 	uint32_t ccm_target_root_clr;
158 	uint32_t ccm_target_root_tog;
159 	uint32_t ccm_misc;
160 	uint32_t ccm_misc_set;
161 	uint32_t ccm_misc_clr;
162 	uint32_t ccm_misc_tog;
163 	uint32_t ccm_post;
164 	uint32_t ccm_post_set;
165 	uint32_t ccm_post_clr;
166 	uint32_t ccm_post_tog;
167 	uint32_t ccm_pre;
168 	uint32_t ccm_pre_set;
169 	uint32_t ccm_pre_clr;
170 	uint32_t ccm_pre_tog;
171 	uint32_t reserved[0x0c];
172 	uint32_t ccm_access_ctrl;
173 	uint32_t ccm_access_ctrl_set;
174 	uint32_t ccm_access_ctrl_clr;
175 	uint32_t ccm_access_ctrl_tog;
176 };
177 
178 #define CCM_TARGET_ROOT_ENABLE		BIT(28)
179 #define CCM_TARGET_MUX(x)		(((x) - 1) << 24)
180 #define CCM_TARGET_PRE_PODF(x)		(((x) - 1) << 16)
181 #define CCM_TARGET_POST_PODF(x)		((x) - 1)
182 
183 /* Target root MUX values - selects the clock source for a block */
184 /* ARM_A7_CLK_ROOT */
185 
186 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_OSC_24M			0
187 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_ARM_PLL			BIT(24)
188 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_ENET_PLL_DIV2		BIT(25)
189 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_DDR_PLL			(BIT(25) | BIT(24))
190 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_SYS_PLL			BIT(26)
191 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_SYS_PLL_PFD0		(BIT(26) | BIT(24))
192 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_AUDIO_PLL			(BIT(26) | BIT(25))
193 #define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
194 
195 /* ARM_M4_CLK_ROOT */
196 
197 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_OSC_24M			0
198 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
199 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_ENET_PLL_DIV4		BIT(25)
200 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_SYS_PLL_PFD2		(BIT(25) | BIT(24))
201 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_DDR_PLL_DIV2		BIT(26)
202 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_AUDIO_PLL			(BIT(26) | BIT(24))
203 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTV_IDEO_PLL			(BIT(26) | BIT(25))
204 #define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL			((BIT(26) | BIT(25) | BIT(24))
205 
206 /* MAIN_AXI_CLK_ROOT */
207 
208 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_OSC_24M			0
209 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD1		BIT(24)
210 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_DDR_PLL_DIV2		BIT(25)
211 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_ENET_PLL_DIV4		(BIT(25) | BIT(24))
212 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD5		BIT(26)
213 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_AUDIO_PLL		(BIT(26) | BIT(24))
214 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
215 #define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD7		((BIT(26) | BIT(25) | BIT(24))
216 
217 /* DISP_AXI_CLK_ROOT */
218 
219 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_OSC_24M			0
220 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD1		BIT(24)
221 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_DDR_PLL_DIV2		BIT(25)
222 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_ENET_PLL_DIV4		(BIT(25) | BIT(24))
223 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD6		BIT(26)
224 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD7		(BIT(26) | BIT(24))
225 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_AUDIO_PLL		(BIT(26) | BIT(25))
226 #define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL		((BIT(26) | BIT(25) | BIT(24))
227 
228 /* ENET_AXI_CLK_ROOT */
229 
230 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_OSC_24M			0
231 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_PFD2		BIT(24)
232 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_DDR_PLL_DIV2		BIT(25)
233 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_ENET_PLL_DIV4		(BIT(25) | BIT(24))
234 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_DIV2		BIT(26)
235 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_AUDIO_PLL		(BIT(26) | BIT(24))
236 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
237 #define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_PFD4		((BIT(26) | BIT(25) | BIT(24))
238 
239 /* NAND_USDHC_BUS_CLK_ROOT */
240 
241 #define CM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_OSC_24M		0
242 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB		BIT(24)
243 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_DDR_PLL_DIV2	BIT(25)
244 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_DIV2	(BIT(25) | BIT(24))
245 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_PFD2_DIV2	BIT(26)
246 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_PFD6	(BIT(26) | BIT(24))
247 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_ENET_PLL_DIV4	(BIT(26) | BIT(25))
248 #define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AUDIO_PLL		((BIT(26) | BIT(25) | BIT(24))
249 
250 /* AHB_CLK_ROOT */
251 
252 #define CCM_TRGT_MUX_AHB_CLK_ROOT_OSC_24M			0
253 #define CCM_TRGT_MUX_AHB_CLK_ROOT_SYS_PLL_PFD2			BIT(24)
254 #define CCM_TRGT_MUX_AHB_CLK_ROOT_DDR_PLL_DIV2			BIT(25)
255 #define CCM_TRGT_MUX_AHB_CLK_ROOT_SYS_PLL_PFD0			(BIT(25) | BIT(24))
256 #define CCM_TRGT_MUX_AHB_CLK_ROOT_ENET_PLL_DIV8			BIT(26)
257 #define CCM_TRGT_MUX_AHB_CLK_ROOT_USB_PLL			(BIT(26) | BIT(24))
258 #define CCM_TRGT_MUX_AHB_CLK_ROOT_AUDIO_PLL			(BIT(26) | BIT(25))
259 #define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL			((BIT(26) | BIT(25) | BIT(24))
260 
261 /* IPG_CLK_ROOT */
262 #define CCM_TRGT_MUX_IPG_CLK_ROOT_AHB_CLK_ROOT			0
263 
264 /* DRAM_PHYM_CLK_ROOT */
265 #define CCM_TRGT_MUX_DRAM_PHYM_CLK_ROOT_DDR_PLL			0
266 #define CCM_TRGT_MUX_DRAM_PHYM_CLK_ROOT_DRAM_PHYM_ALT_CLK_ROOT	BIT(24)
267 
268 /* DRAM_CLK_ROOT */
269 
270 #define CCM_TRGT_MUX_DRAM_CLK_ROOT_DDR_PLL			0
271 #define CCM_TRGT_MUX_DRAM_CLK_ROOT_DRAM_ALT_CLK_ROOT		BIT(24)
272 
273 /* DRAM_PHYM_ALT_CLK_ROOT */
274 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_OSC_24M		0
275 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_DDR_PLL_DIV2	BIT(24)
276 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_SYS_PLL		BIT(25)
277 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_ENET_PLL_DIV2	(BIT(25) | BIT(24))
278 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_USB_PLL		BIT(26)
279 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_SYS_PLL_PFD7	(BIT(26) | BIT(24))
280 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_AUDIO_PLL		(BIT(26) | BIT(25))
281 #define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_VIDEO_PLL		((BIT(26) | BIT(25) | BIT(24))
282 
283 /* DRAM_ALT_CLK_ROOT */
284 
285 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_OSC_24M			0
286 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_DDR_PLL_DIV2		BIT(24)
287 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL			BIT(25)
288 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_ENET_PLL_DIV4		(BIT(25) | BIT(24))
289 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_USB_PLL			BIT(26)
290 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL_PFD0		(BIT(26) | BIT(24))
291 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_AUDIO_PLL		(BIT(26) | BIT(25))
292 #define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL_PFD2		((BIT(26) | BIT(25) | BIT(24))
293 
294 /* USB_HSIC_CLK_ROOT */
295 
296 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_OSC_24M			0
297 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL			BIT(24)
298 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_USB_PLL			BIT(25)
299 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD3		(BIT(25) | BIT(24))
300 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD4		BIT(26)
301 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD5		(BIT(26) | BIT(24))
302 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD6		(BIT(26) | BIT(25))
303 #define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD7		((BIT(26) | BIT(25) | BIT(24))
304 
305 /* LCDIF_PIXEL_CLK_ROOT */
306 
307 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_OSC_24M		0
308 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD5		BIT(24)
309 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_DDR_PLL_DIV2		BIT(25)
310 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_EXT_CLK3		(BIT(25) | BIT(24))
311 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD4		BIT(26)
312 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD2		(BIT(26) | BIT(24))
313 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
314 #define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_USB_PLL		((BIT(26) | BIT(25) | BIT(24))
315 
316 /* MIPI_DSI_CLK_ROOT */
317 
318 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_OSC_24M			0
319 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD5		BIT(24)
320 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD3		BIT(25)
321 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL			(BIT(25) | BIT(24))
322 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD0_DIV2	BIT(26)
323 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_DDR_PLL_DIV2		(BIT(26) | BIT(24))
324 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
325 #define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_AUDIO_PLL		((BIT(26) | BIT(25) | BIT(24))
326 
327 /* MIPI_CSI_CLK_ROOT */
328 
329 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_OSC_24M			0
330 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD4		BIT(24)
331 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD3		BIT(25)
332 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL			(BIT(25) | BIT(24))
333 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD0_DIV2	BIT(26)
334 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_DDR_PLL_DIV2		(BIT(26) | BIT(24))
335 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
336 #define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_AUDIO_PLL		((BIT(26) | BIT(25) | BIT(24))
337 
338 /* MIPI_DPHY_REF_CLK_ROOT */
339 
340 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_OSC_24M		0
341 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_SYS_PLL_DIV4	BIT(24)
342 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_DDR_PLL_DIV2	BIT(25)
343 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_SYS_PLL_PFD5	(BIT(25) | BIT(24))
344 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_REF_1M		BIT(26)
345 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_EXT_CLK2		(BIT(26) | BIT(24))
346 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
347 #define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_EXT_CLK3		((BIT(26) | BIT(25) | BIT(24))
348 
349 /* SAI1_CLK_ROOT */
350 
351 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_OSC_24M			0
352 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_SYS_PLL_PFD2_DIV2		BIT(24)
353 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_AUDIO_PLL			BIT(25)
354 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
355 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_VIDEO_PLL			BIT(26)
356 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_SYS_PLL_PFD4			(BIT(26) | BIT(24))
357 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_ENET_PLL_DIV8		(BIT(26) | BIT(25))
358 #define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2			((BIT(26) | BIT(25) | BIT(24))
359 
360 /* SAI2_CLK_ROOT */
361 
362 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_OSC_24M			0
363 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_SYS_PLL_PFD2_DIV2		BIT(24)
364 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_AUDIO_PLL			BIT(25)
365 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
366 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_VIDEO_PLL			BIT(26)
367 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_SYS_PLL_PFD4			(BIT(26) | BIT(24))
368 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_ENET_PLL_DIV8		(BIT(26) | BIT(25))
369 #define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2			((BIT(26) | BIT(25) | BIT(24))
370 
371 /* SAI3_CLK_ROOT */
372 
373 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_OSC_24M			0
374 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_SYS_PLL_PFD2_DIV2		BIT(24)
375 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_AUDIO_PLL			BIT(25)
376 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
377 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_VIDEO_PLL			BIT(26)
378 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_SYS_PLL_PFD4			(BIT(26) | BIT(24))
379 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_ENET_PLL_DIV8		(BIT(26) | BIT(25))
380 #define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3			((BIT(26) | BIT(25) | BIT(24))
381 
382 /* ENET1_REF_CLK_ROOT */
383 
384 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_OSC_24M			0
385 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV8		BIT(24)
386 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV20		BIT(25)
387 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV40		(BIT(25) | BIT(24))
388 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_SYS_PLL_DIV4		BIT(26)
389 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_AUDIO_PLL		(BIT(26) | BIT(24))
390 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
391 #define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_EXT_CLK4		((BIT(26) | BIT(25) | BIT(24))
392 
393 /* ENET1_TIME_CLK_ROOT */
394 
395 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_OSC_24M		0
396 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
397 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_AUDIO_PLL		BIT(25)
398 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK1		(BIT(25) | BIT(24))
399 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK2		BIT(26)
400 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK3		(BIT(26) | BIT(24))
401 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK4		(BIT(26) | BIT(25))
402 #define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_VIDEO_PLL		((BIT(26) | BIT(25) | BIT(24))
403 
404 /* ENET_PHY_REF_CLK_ROOT */
405 
406 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_OSC_24M		0
407 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV40	BIT(24)
408 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV20	BIT(25)
409 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV8	(BIT(25) | BIT(24))
410 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_DDR_PLL_DIV2		BIT(26)
411 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_AUDIO_PLL		(BIT(26) | BIT(24))
412 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
413 #define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_SYS_PLL_PFD3		((BIT(26) | BIT(25) | BIT(24))
414 
415 /* EIM_CLK_ROOT */
416 
417 #define CCM_TRGT_MUX_EIM_CLK_ROOT_OSC_24M			0
418 #define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD2_DIV2		BIT(24)
419 #define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_DIV4			BIT(25)
420 #define CCM_TRGT_MUX_EIM_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
421 #define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD2			BIT(26)
422 #define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD3			(BIT(26) | BIT(24))
423 #define CCM_TRGT_MUX_EIM_CLK_ROOT_ENET_PLL_DIV8			(BIT(26) | BIT(25))
424 #define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
425 
426 /* NAND_CLK_ROOT */
427 
428 #define CCM_TRGT_MUX_NAND_CLK_ROOT_OSC_24M			0
429 #define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL			BIT(24)
430 #define CCM_TRGT_MUX_NAND_CLK_ROOT_DDR_PLL_DIV2			BIT(25)
431 #define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL_PFD0			(BIT(25) | BIT(24))
432 #define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL_PFD3			BIT(26)
433 #define CCM_TRGT_MUX_NAND_CLK_ROOT_ENET_PLL_DIV2		(BIT(26) | BIT(24))
434 #define CCM_TRGT_MUX_NAND_CLK_ROOT_ENET_PLL_DIV4		(BIT(26) | BIT(25))
435 #define CCM_TRGT_MUX_NAND_CLK_ROOT_VIDEO_PLL			((BIT(26) | BIT(25) | BIT(24))
436 
437 /* QSPI_CLK_ROOT */
438 
439 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_OSC_24M			0
440 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD4			BIT(24)
441 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_DDR_PLL_DIV2			BIT(25)
442 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_ENET_PLL_DIV2		(BIT(25) | BIT(24))
443 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD3			BIT(26)
444 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD2			(BIT(26) | BIT(24))
445 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD6			(BIT(26) | BIT(25))
446 #define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD7			((BIT(26) | BIT(25) | BIT(24))
447 
448 /* USDHC1_CLK_ROOT */
449 
450 #define CM_TRGT_MUX_USDHC1_CLK_ROOT_OSC_24M			0
451 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD0		BIT(24)
452 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_DDR_PLL_DIV2		BIT(25)
453 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_ENET_PLL_DIV2		(BIT(25) | BIT(24))
454 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD4		BIT(26)
455 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD2		(BIT(26) | BIT(24))
456 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD6		(BIT(26) | BIT(25))
457 #define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD7		((BIT(26) | BIT(25) | BIT(24))
458 
459 /* USDHC2_CLK_ROOT */
460 
461 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_OSC_24M			0
462 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD0		BIT(24)
463 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_DDR_PLL_DIV2		BIT(25)
464 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_ENET_PLL_DIV2		(BIT(25) | BIT(24))
465 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD4		BIT(26)
466 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD2		(BIT(26) | BIT(24))
467 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD6		(BIT(26) | BIT(25))
468 #define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD7		((BIT(26) | BIT(25) | BIT(24))
469 
470 /* USDHC3_CLK_ROOT */
471 
472 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_OSC_24M			0
473 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD0		BIT(24)
474 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_DDR_PLL_DIV2		BIT(25)
475 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_ENET_PLL_DIV2		(BIT(25) | BIT(24))
476 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD4		BIT(26)
477 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD2		(BIT(26) | BIT(24))
478 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD6		(BIT(26) | BIT(25))
479 #define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD7		((BIT(26) | BIT(25) | BIT(24))
480 
481 /* CAN1_CLK_ROOT */
482 
483 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_OSC_24M			0
484 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_SYS_PLL_DIV4			BIT(24)
485 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_DDR_PLL_DIV2			BIT(25)
486 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_SYS_PLL			(BIT(25) | BIT(24))
487 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_ENET_PLL_DIV25		BIT(26)
488 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_USB_PLL			(BIT(26) | BIT(24))
489 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK1			(BIT(26) | BIT(25))
490 #define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4			((BIT(26) | BIT(25) | BIT(24))
491 
492 /* CAN2_CLK_ROOT */
493 
494 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_OSC_24M			0
495 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_SYS_PLL_DIV4			BIT(24)
496 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_DDR_PLL_DIV2			BIT(25)
497 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_SYS_PLL			(BIT(25) | BIT(24))
498 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_ENET_PLL_DIV25		BIT(26)
499 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_USB_PLL			(BIT(26) | BIT(24))
500 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_EXT_CLK1			(BIT(26) | BIT(25))
501 #define CCM_TRGT_MUX_CAN2_CLK_ROOT_EXT_CLK3			((BIT(26) | BIT(25) | BIT(24))
502 
503 /* I2C1_CLK_ROOT */
504 
505 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_OSC_24M			0
506 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_SYS_PLL_DIV4			BIT(24)
507 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_ENET_PLL_DIV20		BIT(25)
508 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
509 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_AUDIO_PLL			BIT(26)
510 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_VIDEO_PLL			(BIT(26) | BIT(24))
511 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_USB_PLL			(BIT(26) | BIT(25))
512 #define CCM_TRGT_MUX_I2C1_CLK_ROOT_SYS_PLL_PFD2_DIV2		((BIT(26) | BIT(25) | BIT(24))
513 
514 /* I2C2_CLK_ROOT */
515 
516 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_OSC_24M			0
517 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_SYS_PLL_DIV4			BIT(24)
518 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_ENET_PLL_DIV20		BIT(25)
519 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
520 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_AUDIO_PLL			BIT(26)
521 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_VIDEO_PLL			(BIT(26) | BIT(24))
522 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_USB_PLL			(BIT(26) | BIT(25))
523 #define CCM_TRGT_MUX_I2C2_CLK_ROOT_SYS_PLL_PFD2_DIV2		((BIT(26) | BIT(25) | BIT(24))
524 
525 /* I2C3_CLK_ROOT */
526 
527 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_OSC_24M			0
528 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_SYS_PLL_DIV4			BIT(24)
529 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_ENET_PLL_DIV20		BIT(25)
530 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
531 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_AUDIO_PLL			BIT(26)
532 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_VIDEO_PLL			(BIT(26) | BIT(24))
533 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_USB_PLL			(BIT(26) | BIT(25))
534 #define CCM_TRGT_MUX_I2C3_CLK_ROOT_SYS_PLL_PFD2_DIV2		((BIT(26) | BIT(25) | BIT(24))
535 
536 /* I2C4_CLK_ROOT */
537 
538 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_OSC_24M			0
539 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_SYS_PLL_DIV4			BIT(24)
540 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_ENET_PLL_DIV20		BIT(25)
541 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
542 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_AUDIO_PLL			BIT(26)
543 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_VIDEO_PLL			(BIT(26) | BIT(24))
544 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_USB_PLL			(BIT(26) | BIT(25))
545 #define CCM_TRGT_MUX_I2C4_CLK_ROOT_SYS_PLL_PFD2_DIV2		((BIT(26) | BIT(25) | BIT(24))
546 
547 /* UART1_CLK_ROOT */
548 
549 #define CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M			0
550 #define CCM_TRGT_MUX_UART1_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
551 #define CCM_TRGT_MUX_UART1_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
552 #define CCM_TRGT_MUX_UART1_CLK_ROOT_ENET_PLL_DIV10		(BIT(25) | BIT(24))
553 #define CCM_TRGT_MUX_UART1_CLK_ROOT_SYS_PLL			BIT(26)
554 #define CCM_TRGT_MUX_UART1_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(24))
555 #define CCM_TRGT_MUX_UART1_CLK_ROOT_EXT_CLK4			(BIT(26) | BIT(25))
556 #define CCM_TRGT_MUX_UART1_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
557 
558 /* UART2_CLK_ROOT */
559 
560 #define CCM_TRGT_MUX_UART2_CLK_ROOT_OSC_24M			0
561 #define CCM_TRGT_MUX_UART2_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
562 #define CCM_TRGT_MUX_UART2_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
563 #define CCM_TRGT_MUX_UART2_CLK_ROOT_ENET_PLL_DIV10		(BIT(25) | BIT(24))
564 #define CCM_TRGT_MUX_UART2_CLK_ROOT_SYS_PLL			BIT(26)
565 #define CCM_TRGT_MUX_UART2_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(24))
566 #define CCM_TRGT_MUX_UART2_CLK_ROOT_EXT_CLK3			(BIT(26) | BIT(25))
567 #define CCM_TRGT_MUX_UART2_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
568 
569 /* UART3_CLK_ROOT */
570 
571 #define CCM_TRGT_MUX_UART3_CLK_ROOT_OSC_24M			0
572 #define CCM_TRGT_MUX_UART3_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
573 #define CCM_TRGT_MUX_UART3_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
574 #define CCM_TRGT_MUX_UART3_CLK_ROOT_ENET_PLL_DIV10		(BIT(25) | BIT(24))
575 #define CCM_TRGT_MUX_UART3_CLK_ROOT_SYS_PLL			BIT(26)
576 #define CCM_TRGT_MUX_UART3_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(24))
577 #define CCM_TRGT_MUX_UART3_CLK_ROOT_EXT_CLK4			(BIT(26) | BIT(25))
578 #define CCM_TRGT_MUX_UART3_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
579 
580 /* UART4_CLK_ROOT */
581 
582 #define CCM_TRGT_MUX_UART4_CLK_ROOT_OSC_24M			0
583 #define CCM_TRGT_MUX_UART4_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
584 #define CCM_TRGT_MUX_UART4_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
585 #define CCM_TRGT_MUX_UART4_CLK_ROOT_ENET_PLL_DIV10		(BIT(25) | BIT(24))
586 #define CCM_TRGT_MUX_UART4_CLK_ROOT_SYS_PLL			BIT(26)
587 #define CCM_TRGT_MUX_UART4_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(24))
588 #define CCM_TRGT_MUX_UART4_CLK_ROOT_EXT_CLK3			(BIT(26) | BIT(25))
589 #define CCM_TRGT_MUX_UART4_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
590 
591 /* UART5_CLK_ROOT */
592 
593 #define CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M			0
594 #define CCM_TRGT_MUX_UART5_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
595 #define CCM_TRGT_MUX_UART5_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
596 #define CCM_TRGT_MUX_UART5_CLK_ROOT_ENET_PLL_DIV10		(BIT(25) | BIT(24))
597 #define CCM_TRGT_MUX_UART5_CLK_ROOT_SYS_PLL			BIT(26)
598 #define CCM_TRGT_MUX_UART5_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(24))
599 #define CCM_TRGT_MUX_UART5_CLK_ROOT_EXT_CLK4			(BIT(26) | BIT(25))
600 #define CCM_TRGT_MUX_UART5_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
601 
602 /* UART6_CLK_ROOT */
603 
604 #define CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M			0
605 #define CCM_TRGT_MUX_UART6_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
606 #define CCM_TRGT_MUX_UART6_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
607 #define CCM_TRGT_MUX_UART6_CLK_ROOT_ENET_PLL_DIV10		(BIT(25) | BIT(24))
608 #define CCM_TRGT_MUX_UART6_CLK_ROOT_SYS_PLL			BIT(26)
609 #define CCM_TRGT_MUX_UART6_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(24))
610 #define CCM_TRGT_MUX_UART6_CLK_ROOT_EXT_CLK3			(BIT(26) | BIT(25))
611 #define CCM_TRGT_MUX_UART6_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
612 
613 /* UART7_CLK_ROOT */
614 
615 #define CCM_TRGT_MUX_UART7_CLK_ROOT_OSC_24M			0
616 #define CCM_TRGT_MUX_UART7_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
617 #define CCM_TRGT_MUX_UART7_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
618 #define CCM_TRGT_MUX_UART7_CLK_ROOT_ENET_PLL_DIV10		(BIT(25) | BIT(24))
619 #define CCM_TRGT_MUX_UART7_CLK_ROOT_SYS_PLL			BIT(26)
620 #define CCM_TRGT_MUX_UART7_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(24))
621 #define CCM_TRGT_MUX_UART7_CLK_ROOT_EXT_CLK4			(BIT(26) | BIT(25))
622 #define CCM_TRGT_MUX_UART7_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
623 
624 /* ECSPI1_CLK_ROOT */
625 
626 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_OSC_24M			0
627 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
628 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
629 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_DIV4		(BIT(25) | BIT(24))
630 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL			BIT(26)
631 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_PFD4		(BIT(26) | BIT(24))
632 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_ENET_PLL_DIV4		(BIT(26) | BIT(25))
633 #define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
634 
635 /* ECSPI2_CLK_ROOT */
636 
637 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_OSC_24M			0
638 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
639 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
640 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_DIV4		(BIT(25) | BIT(24))
641 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL			BIT(26)
642 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_PFD4		(BIT(26) | BIT(24))
643 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_ENET_PLL_DIV4		(BIT(26) | BIT(25))
644 #define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
645 
646 /* ECSPI3_CLK_ROOT */
647 
648 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_OSC_24M			0
649 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
650 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
651 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_DIV4		(BIT(25) | BIT(24))
652 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL			BIT(26)
653 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_PFD4		(BIT(26) | BIT(24))
654 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_ENET_PLL_DIV4		(BIT(26) | BIT(25))
655 #define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
656 
657 /* ECSPI4_CLK_ROOT */
658 
659 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_OSC_24M			0
660 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_DIV2		BIT(24)
661 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_ENET_PLL_DIV25		BIT(25)
662 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_DIV4		(BIT(25) | BIT(24))
663 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL			BIT(26)
664 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_PFD4		(BIT(26) | BIT(24))
665 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_ENET_PLL_DIV4		(BIT(26) | BIT(25))
666 #define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
667 
668 /* PWM1_CLK_ROOT */
669 
670 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_OSC_24M			0
671 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
672 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_SYS_PLL_DIV4			BIT(25)
673 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
674 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_AUDIO_PLL			BIT(26)
675 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_EXT_CLK1			(BIT(26) | BIT(24))
676 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_REF_1M			(BIT(26) | BIT(25))
677 #define CCM_TRGT_MUX_PWM1_CLK_ROOT_VIDEO_PLL			((BIT(26) | BIT(25) | BIT(24))
678 
679 /* PWM2_CLK_ROOT */
680 
681 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_OSC_24M			0
682 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
683 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_SYS_PLL_DIV4			BIT(25)
684 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
685 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_AUDIO_PLL			BIT(26)
686 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_EXT_CLK1			(BIT(26) | BIT(24))
687 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_REF_1M			(BIT(26) | BIT(25))
688 #define CCM_TRGT_MUX_PWM2_CLK_ROOT_VIDEO_PLL			((BIT(26) | BIT(25) | BIT(24))
689 
690 /* PWM3_CLK_ROOT */
691 
692 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_OSC_24M			0
693 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
694 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_SYS_PLL_DIV4			BIT(25)
695 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
696 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_AUDIO_PLL			BIT(26)
697 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(24))
698 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_REF_1M			(BIT(26) | BIT(25))
699 #define CCM_TRGT_MUX_PWM3_CLK_ROOT_VIDEO_PLL			((BIT(26) | BIT(25) | BIT(24))
700 
701 /* PWM4_CLK_ROOT */
702 
703 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_OSC_24M			0
704 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
705 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_SYS_PLL_DIV4			BIT(25)
706 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
707 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_AUDIO_PLL			BIT(26)
708 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(24))
709 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_REF_1M			(BIT(26) | BIT(25))
710 #define CCM_TRGT_MUX_PWM4_CLK_ROOT_VIDEO_PLL			((BIT(26) | BIT(25) | BIT(24))
711 
712 /* FLEXTIMER1_CLK_ROOT */
713 
714 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_OSC_24M		0
715 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
716 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_SYS_PLL_DIV4		BIT(25)
717 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
718 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_AUDIO_PLL		BIT(26)
719 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_EXT_CLK3		(BIT(26) | BIT(24))
720 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_REF_1M			(BIT(26) | BIT(25))
721 #define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_VIDEO_PLL		((BIT(26) | BIT(25) | BIT(24))
722 
723 /* FLEXTIMER2_CLK_ROOT */
724 
725 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_OSC_24M		0
726 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
727 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_SYS_PLL_DIV4		BIT(25)
728 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
729 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_AUDIO_PLL		BIT(26)
730 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_EXT_CLK3		(BIT(26) | BIT(24))
731 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_REF_1M			(BIT(26) | BIT(25))
732 #define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_VIDEO_PLL		((BIT(26) | BIT(25) | BIT(24))
733 
734 /* Target SIM1_CLK_ROOT */
735 
736 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_OSC_24M			0
737 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_PFD2_DIV2		BIT(24)
738 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_DIV4			BIT(25)
739 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
740 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_USB_PLL			BIT(26)
741 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_AUDIO_PLL			(BIT(26) | BIT(24))
742 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_ENET_PLL_DIV8		(BIT(26) | BIT(25))
743 #define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_PFD7			((BIT(26) | BIT(25) | BIT(24))
744 
745 /* Target SIM2_CLK_ROOT */
746 
747 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_OSC_24M			0
748 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_PFD2_DIV2		BIT(24)
749 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_DIV4			BIT(25)
750 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
751 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_USB_PLL			BIT(26)
752 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_VIDEO_PLL			(BIT(26) | BIT(24))
753 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_ENET_PLL_DIV8		(BIT(26) | BIT(25))
754 #define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_PFD7			((BIT(26) | BIT(25) | BIT(24))
755 
756 /* Target GPT1_CLK_ROOT */
757 
758 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_OSC_24M			0
759 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
760 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_SYS_PLL_PFD0			BIT(25)
761 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
762 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_VIDEO_PLL			BIT(26)
763 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_REF_1M			(BIT(26) | BIT(24))
764 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_AUDIO_PLL			(BIT(26) | BIT(25))
765 #define CCM_TRGT_MUX_GPT1_CLK_ROOT_EXT_CLK1			((BIT(26) | BIT(25) | BIT(24))
766 
767 /* Target GPT2_CLK_ROOT */
768 
769 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_OSC_24M			0
770 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
771 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_SYS_PLL_PFD0			BIT(25)
772 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
773 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_VIDEO_PLL			BIT(26)
774 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_REF_1M			(BIT(26) | BIT(24))
775 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_AUDIO_PLL			(BIT(26) | BIT(25))
776 #define CCM_TRGT_MUX_GPT2_CLK_ROOT_EXT_CLK2			((BIT(26) | BIT(25) | BIT(24))
777 
778 /* Target GPT3_CLK_ROOT */
779 
780 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_OSC_24M			0
781 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
782 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_SYS_PLL_PFD0			BIT(25)
783 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
784 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_VIDEO_PLL			BIT(26)
785 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_REF_1M			(BIT(26) | BIT(24))
786 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_AUDIO_PLL			(BIT(26) | BIT(25))
787 #define CCM_TRGT_MUX_GPT3_CLK_ROOT_EXT_CLK3			((BIT(26) | BIT(25) | BIT(24))
788 
789 /*Target GPT4_CLK_ROOT */
790 
791 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_OSC_24M			0
792 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_ENET_PLL_DIV10		BIT(24)
793 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_SYS_PLL_PFD0			BIT(25)
794 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_ENET_PLL_DIV25		(BIT(25) | BIT(24))
795 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_VIDEO_PLL			BIT(26)
796 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_REF_1M			(BIT(26) | BIT(24))
797 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_AUDIO_PLL			(BIT(26) | BIT(25))
798 #define CCM_TRGT_MUX_GPT4_CLK_ROOT_EXT_CLK4			((BIT(26) | BIT(25) | BIT(24))
799 
800 /* Target TRACE_CLK_ROOT */
801 
802 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_OSC_24M			0
803 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_SYS_PLL_PFD2_DIV2		BIT(24)
804 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_SYS_PLL_DIV4		BIT(25)
805 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_DDR_PLL_DIV2		(BIT(25) | BIT(24))
806 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_ENET_PLL_DIV8		BIT(26)
807 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_USB_PLL			(BIT(26) | BIT(24))
808 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_EXT_CLK2			(BIT(26) | BIT(25))
809 #define CCM_TRGT_MUX_TRACE_CLK_ROOT_EXT_CLK3			((BIT(26) | BIT(25) | BIT(24))
810 
811 /* Target WDOG_CLK_ROOT */
812 
813 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M			0
814 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD2_DIV2		BIT(24)
815 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_DIV4			BIT(25)
816 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_DDR_PLL_DIV2			(BIT(25) | BIT(24))
817 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_ENET_PLL_DIV8		BIT(26)
818 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_USB_PLL			(BIT(26) | BIT(24))
819 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_REF_1M			(BIT(26) | BIT(25))
820 #define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD1_DIV2		((BIT(26) | BIT(25) | BIT(24))
821 #define WDOG_DEFAULT_CLK_SELECT					(CCM_TARGET_ROOT_ENABLE |\
822 								CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
823 
824 /* Target CSI_MCLK_CLK_ROOT */
825 
826 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_OSC_24M			0
827 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_SYS_PLL_PFD2_DIV2	BIT(24)
828 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_SYS_PLL_DIV4		BIT(25)
829 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_DDR_PLL_DIV2		(BIT(25) | BIT(24))
830 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_ENET_PLL_DIV8		BIT(26)
831 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_AUDIO_PLL		(BIT(26) | BIT(24))
832 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
833 #define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_USB_PLL			((BIT(26) | BIT(25) | BIT(24))
834 
835 /* Target AUDIO_MCLK_CLK_ROOT */
836 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_OSC_24M		0
837 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_SYS_PLL_PFD2_DIV2	BIT(24)
838 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_SYS_PLL_DIV4		BIT(25)
839 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_DDR_PLL_DIV2		(BIT(25) | BIT(24))
840 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_ENET_PLL_DIV8		BIT(26)
841 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_AUDIO_PLL		(BIT(26) | BIT(24))
842 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_VIDEO_PLL		(BIT(26) | BIT(25))
843 #define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_USB_PLL		((BIT(26) | BIT(25) | BIT(24))
844 
845 /* Target CCM_CLKO1 */
846 #define CCM_TRGT_MUX_CCM_CLKO1_OSC_24M				0
847 #define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL				BIT(24)
848 #define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_DIV2			BIT(25)
849 #define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_PFD0_DIV2		(BIT(25) | BIT(24))
850 #define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_PFD3			BIT(26)
851 #define CCM_TRGT_MUX_CCM_CLKO1_ENET_PLL_DIV2			(BIT(26) | BIT(24))
852 #define CCM_TRGT_MUX_CCM_CLKO1_DDR_PLL_DIV2			(BIT(26) | BIT(25))
853 #define CCM_TRGT_MUX_CCM_CLKO1_REF_1M				((BIT(26) | BIT(25) | BIT(24))
854 
855 /* Target CCM_CLKO2 */
856 #define CCM_TRGT_MUX_CCM_CLKO2_OSC_24M				0
857 #define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_DIV2			BIT(24)
858 #define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD0			BIT(25)
859 #define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD1_DIV2		(BIT(25) | BIT(24))
860 #define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD4			BIT(26)
861 #define CCM_TRGT_MUX_CCM_CLKO2_AUDIO_PLL			(BIT(26) | BIT(24))
862 #define CCM_TRGT_MUX_CCM_CLKO2_VIDEO_PLL			(BIT(26) | BIT(25))
863 #define CCM_TRGT_MUX_CCM_CLKO2_OSC_32K				((BIT(26) | BIT(25) | BIT(24))
864 
865 /*
866  * See Table 5-11 in i.MX7 Solo Reference manual rev 0.1
867  * The indices must be calculated by dividing the offset by
868  * sizeof (struct ccm_target_root_ctrl) => 0x80 bytes for each index
869  */
870 enum {
871 	CCM_TRT_ID_ARM_A7_CLK_ROOT = 0,
872 	CCM_TRT_ID_ARM_M4_CLK_ROOT = 1,
873 	CCM_TRT_ID_MAIN_AXI_CLK_ROOT = 16,
874 	CCM_TRT_ID_DISP_AXI_CLK_ROOT = 17,
875 	CCM_TRT_ID_ENET_AXI_CLK_ROOT = 18,
876 	CCM_TRT_ID_NAND_USDHC_BUS_CLK_ROOT = 19,
877 	CCM_TRT_ID_AHB_CLK_ROOT = 32,
878 	CCM_TRT_ID_IPG_CLK_ROOT = 33,
879 	CCM_TRT_ID_DRAM_PHYM_CLK_ROOT = 48,
880 	CCM_TRT_ID_DRAM_CLK_ROOT = 49,
881 	CCM_TRT_ID_DRAM_PHYM_ALT_CLK_ROOT = 64,
882 	CCM_TRT_ID_DRAM_ALT_CLK_ROOT = 65,
883 	CCM_TRT_ID_USB_HSIC_CLK_ROOT = 66,
884 	CCM_TRT_ID_LCDIF_PIXEL_CLK_ROOT = 70,
885 	CCM_TRT_ID_MIPI_DSI_CLK_ROOT = 71,
886 	CCM_TRT_ID_MIPI_CSI_CLK_ROOT = 72,
887 	CCM_TRT_ID_MIPI_DPHY_REF_CLK_ROOT = 73,
888 	CCM_TRT_ID_SAI1_CLK_ROOT = 74,
889 	CCM_TRT_ID_SAI2_CLK_ROOT = 75,
890 	CCM_TRT_ID_SAI3_CLK_ROOT = 76,
891 	CCM_TRT_ID_ENET1_REF_CLK_ROOT = 78,
892 	CCM_TRT_ID_ENET1_TIME_CLK_ROOT = 79,
893 	CCM_TRT_ID_ENET_PHY_REF_CLK_ROOT = 82,
894 	CCM_TRT_ID_EIM_CLK_ROOT = 83,
895 	CCM_TRT_ID_NAND_CLK_ROOT = 84,
896 	CCM_TRT_ID_QSPI_CLK_ROOT = 85,
897 	CCM_TRT_ID_USDHC1_CLK_ROOT = 86,
898 	CCM_TRT_ID_USDHC2_CLK_ROOT = 87,
899 	CCM_TRT_ID_USDHC3_CLK_ROOT = 88,
900 	CCM_TRT_ID_CAN1_CLK_ROOT = 89,
901 	CCM_TRT_ID_CAN2_CLK_ROOT = 90,
902 	CCM_TRT_ID_I2C1_CLK_ROOT = 91,
903 	CCM_TRT_ID_I2C2_CLK_ROOT = 92,
904 	CCM_TRT_ID_I2C3_CLK_ROOT = 93,
905 	CCM_TRT_ID_I2C4_CLK_ROOT = 94,
906 	CCM_TRT_ID_UART1_CLK_ROOT = 95,
907 	CCM_TRT_ID_UART2_CLK_ROOT = 96,
908 	CCM_TRT_ID_UART3_CLK_ROOT = 97,
909 	CCM_TRT_ID_UART4_CLK_ROOT = 98,
910 	CCM_TRT_ID_UART5_CLK_ROOT = 99,
911 	CCM_TRT_ID_UART6_CLK_ROOT = 100,
912 	CCM_TRT_ID_UART7_CLK_ROOT = 101,
913 	CCM_TRT_ID_ECSPI1_CLK_ROOT = 102,
914 	CCM_TRT_ID_ECSPI2_CLK_ROOT = 103,
915 	CCM_TRT_ID_ECSPI3_CLK_ROOT = 104,
916 	CCM_TRT_ID_ECSPI4_CLK_ROOT = 105,
917 	CCM_TRT_ID_PWM1_CLK_ROOT = 106,
918 	CCM_TRT_ID_PWM2_CLK_ROOT = 107,
919 	CCM_TRT_ID_PWM3_CLK_ROOT = 108,
920 	CCM_TRT_ID_PWM4_CLK_ROOT = 109,
921 	CCM_TRT_ID_FLEXTIMER1_CLK_ROOT = 110,
922 	CCM_TRT_ID_FLEXTIMER2_CLK_ROOT = 111,
923 	CCM_TRT_ID_SIM1_CLK_ROOT = 112,
924 	CCM_TRT_ID_SIM2_CLK_ROOT = 113,
925 	CCM_TRT_ID_GPT1_CLK_ROOT = 114,
926 	CCM_TRT_ID_GPT2_CLK_ROOT = 115,
927 	CCM_TRT_ID_GPT3_CLK_ROOT = 116,
928 	CCM_TRT_ID_GPT4_CLK_ROOT = 117,
929 	CCM_TRT_ID_TRACE_CLK_ROOT = 118,
930 	CCM_TRT_ID_WDOG_CLK_ROOT = 119,
931 	CCM_TRT_ID_CSI_MCLK_CLK_ROOT = 120,
932 	CCM_TRT_ID_AUDIO_MCLK_CLK_ROOT = 121,
933 	CCM_TRT_ID_CCM_CLKO1 = 123,
934 	CCM_TRT_ID_CCM_CLKO2 = 124,
935 };
936 
937 #define CCM_MISC_VIOLATE		BIT(8)
938 #define CCM_MISC_TIMEOUT		BIT(4)
939 #define CCM_MISC_AUTHEN_FAIL		BIT(0)
940 
941 #define CCM_POST_BUSY2			BIT(31)
942 #define CCM_POST_SELECT_BRANCH_A	BIT(28)
943 #define CCM_POST_BUSY1			BIT(7)
944 #define CCM_POST_POST_PODF(x)		((x) - 1)
945 
946 #define CCM_PRE_BUSY4			BIT(31)
947 #define CCM_PRE_ENABLE_A		BIT(28)
948 #define CCM_PRE_MUX_A(x)		(((x) - 1) << 24)
949 #define CCM_PRE_BUSY3			BIT(19)
950 #define CCM_PRE_PODF_A(x)		(((x) - 1) << 16)
951 #define CCM_PRE_BUSY1			BIT(15)
952 #define CCM_PRE_ENABLE_B		BIT(12)
953 #define CCM_PRE_MUX_B(x)		(((x) - 1) << 8)
954 #define CCM_PRE_BUSY0			BIT(3)
955 #define CCM_PRE_POST_PODF(x)		((x) - 1)
956 
957 #define CCM_ACCESS_CTRL_LOCK		BIT(31)
958 #define CCM_ACCESS_SEMA_ENABLE		BIT(28)
959 #define CCM_ACCESS_DOM3_WHITELIST	BIT(27)
960 #define CCM_ACCESS_DOM2_WHITELIST	BIT(26)
961 #define CCM_ACCESS_DOM1_WHITELIST	BIT(25)
962 #define CCM_ACCESS_DOM0_WHITELIST	BIT(24)
963 #define CCM_ACCESS_MUTEX		BIT(20)
964 #define CCM_ACCESS_OWNER_ID(x)		((x) << 16)
965 #define CCM_ACCESS_DOM3_INFO(x)		((x) << 12)
966 #define CCM_ACCESS_DOM2_INFO(x)		((x) << 8)
967 #define CCM_ACCESS_DOM1_INFO(x)		((x) << 4)
968 #define CCM_ACCESS_DOM0_INFO(x)		(x)
969 
970 #define CCM_PLL_CTRL_NUM	0x21
971 #define CCM_CLK_GATE_CTRL_NUM	0xbf
972 #define CCM_ROOT_CTRL_NUM	0x79
973 
974 struct ccm {
975 	uint32_t ccm_gpr0;
976 	uint32_t ccm_gpr0_set;
977 	uint32_t ccm_gpr0_clr;
978 	uint32_t ccm_grp0_tog;
979 	uint32_t reserved[0x1fc];
980 	struct ccm_pll_ctrl ccm_pll_ctrl[CCM_PLL_CTRL_NUM];
981 	uint32_t reserved1[0xd7c];
982 	struct ccm_clk_gate_ctrl ccm_clk_gate_ctrl[CCM_CLK_GATE_CTRL_NUM];
983 	uint32_t reserved2[0xd04];
984 	struct ccm_target_root_ctrl ccm_root_ctrl[CCM_ROOT_CTRL_NUM];
985 };
986 
987 void imx_clock_target_set(unsigned int id, uint32_t val);
988 void imx_clock_target_clr(unsigned int id, uint32_t val);
989 void imx_clock_gate_enable(unsigned int id, bool enable);
990 
991 void imx_clock_init(void);
992 
993 void imx_clock_enable_uart(unsigned int uart_id, uint32_t uart_clk_en_bits);
994 void imx_clock_disable_uart(unsigned int uart_id);
995 void imx_clock_enable_usdhc(unsigned int usdhc_id, uint32_t usdhc_clk_en_bits);
996 void imx_clock_set_wdog_clk_root_bits(uint32_t wdog_clk_root_en_bits);
997 void imx_clock_enable_wdog(unsigned int wdog_id);
998 void imx_clock_disable_wdog(unsigned int wdog_id);
999 void imx_clock_enable_usb(unsigned int usb_id);
1000 void imx_clock_disable_usb(unsigned int usb_id);
1001 void imx_clock_set_usb_clk_root_bits(uint32_t usb_clk_root_en_bits);
1002 
1003 #endif /* IMX_CLOCK_H */
1004