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Searched refs:class_sizes (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_fs_reg_allocate.cpp117 int class_sizes[MAX_VGRF_SIZE]; in brw_alloc_reg_set() local
119 class_sizes[i] = i + 1; in brw_alloc_reg_set()
139 ra_reg_count += (base_reg_count - (class_sizes[i] - 1)) / 2; in brw_alloc_reg_set()
141 ra_reg_count += base_reg_count - (class_sizes[i] - 1); in brw_alloc_reg_set()
144 class_to_ra_reg_range[class_sizes[i]] = ra_reg_count; in brw_alloc_reg_set()
177 class_reg_count = (base_reg_count - (class_sizes[i] - 1)) / 2; in brw_alloc_reg_set()
183 q_values[i][j] = (class_sizes[i] + 1) / 2 + in brw_alloc_reg_set()
184 (class_sizes[j] + 1) / 2 - 1; in brw_alloc_reg_set()
186 class_reg_count = base_reg_count - (class_sizes[i] - 1); in brw_alloc_reg_set()
212 q_values[i][j] = class_sizes[i] + class_sizes[j] - 1; in brw_alloc_reg_set()
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Dbrw_vec4_reg_allocate.cpp102 int class_sizes[MAX_VGRF_SIZE]; in brw_vec4_alloc_reg_set() local
105 class_sizes[i] = i + 1; in brw_vec4_alloc_reg_set()
110 ra_reg_count += base_reg_count - (class_sizes[i] - 1); in brw_vec4_alloc_reg_set()
128 int class_reg_count = base_reg_count - (class_sizes[i] - 1); in brw_vec4_alloc_reg_set()
139 base_reg < j + class_sizes[i]; in brw_vec4_alloc_reg_set()
154 q_values[i][j] = class_sizes[i] + class_sizes[j] - 1; in brw_vec4_alloc_reg_set()
/external/mesa3d/src/freedreno/ir3/
Dir3_ra_regset.c44 for (unsigned br = j; br < j + class_sizes[i]; br++) { in setup_conflicts()
228 if (class_sizes[i] >= sz) in ra_size_to_class()
247 return class_sizes[class]; in ra_class_to_size()
Dir3_ra.h35 static const unsigned class_sizes[] = { variable
40 #define class_count ARRAY_SIZE(class_sizes)
67 return (NUM_REGS - (class_sizes[i] - 1)); in CLASS_REGS()
Dir3_ra.c1305 unsigned reglen = class_sizes[id->cls]; in assign_arr_base()
/external/mesa3d/docs/relnotes/
D7.10.rst1207 - i965: Set class_sizes[] for the aligned reg pair class.