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Searched refs:clk (Results 1 – 25 of 94) sorted by relevance

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/external/OpenCSD/decoder/tests/snapshots-ete/002-ack_test_scr/
Dtest_TARMAC2 0 clk cpu0 R cpsr 000003cd
3 1 clk cpu0 IT (1) 10300000 14004000 O EL3h_s : B 0x10310000
4 2 clk cpu0 IT (2) 10310000 d2b01000 O EL3h_s : MOV x0,#0x80800000
5 2 clk cpu0 R X0 0000000080800000
6 3 clk cpu0 IT (3) 10310004 d51e2040 O EL3h_s : MSR TCR_EL3,x0
7 3 clk cpu0 R TCR_EL3 00000000:80800000
8 4 clk cpu0 IT (4) 10310008 d5033fdf O EL3h_s : ISB
9 4 clk cpu0 R PMSCR_EL1 00000000
10 4 clk cpu0 R PMSCR_EL2 00000000
11 4 clk cpu0 R PMSICR_EL1 00000000
[all …]
/external/walt/android/WALT/app/src/main/jni/
Dsync_clock.c130 int send_cmd(struct clock_connection *clk, char cmd) { in send_cmd() argument
131 return bulk_talk(clk->fd, clk->endpoint_out, &cmd, 1); in send_cmd()
135 int send_async(struct clock_connection *clk, char cmd) { in send_async() argument
136 return send_char_async(clk->fd, clk->endpoint_out, cmd, NULL); in send_async()
140 int bulk_read(struct clock_connection *clk) { in bulk_read() argument
141 memset(clk->buffer, 0, sizeof(clk->buffer)); in bulk_read()
142 int ret = bulk_talk(clk->fd, clk->endpoint_in, clk->buffer, sizeof(clk->buffer)); in bulk_read()
147 int micros(struct clock_connection *clk) { in micros() argument
148 return uptimeMicros() - clk->t_base; in micros()
153 void flush_incoming(struct clock_connection *clk) { in flush_incoming() argument
[all …]
Dsync_clock_linux.c58 struct clock_connection clk; in main() local
59 clk.fd = fd; in main()
60 clk.endpoint_in = ep_in; in main()
61 clk.endpoint_out = ep_out; in main()
63 sync_clocks(&clk); in main()
67 (long long int)clk.t_base, clk.minE, clk.maxE); in main()
70 update_bounds(&clk); in main()
74 (long long int)(clk.t_base), clk.minE, clk.maxE in main()
Dsync_clock_jni.c27 struct clock_connection clk; variable
37 clk.fd = (int)fd; in Java_org_chromium_latency_walt_WaltUsbConnection_syncClock__III()
38 clk.endpoint_in = (int)endpoint_in; in Java_org_chromium_latency_walt_WaltUsbConnection_syncClock__III()
39 clk.endpoint_out = (int)endpoint_out; in Java_org_chromium_latency_walt_WaltUsbConnection_syncClock__III()
40 clk.t_base = 0; in Java_org_chromium_latency_walt_WaltUsbConnection_syncClock__III()
41 sync_clocks(&clk); in Java_org_chromium_latency_walt_WaltUsbConnection_syncClock__III()
44 int64_t t_base = clk.t_base; in Java_org_chromium_latency_walt_WaltUsbConnection_syncClock__III()
50 update_bounds(&clk); in Java_org_chromium_latency_walt_WaltUsbConnection_updateBounds()
55 return clk.minE; in Java_org_chromium_latency_walt_WaltUsbConnection_getMinE()
61 return clk.maxE; in Java_org_chromium_latency_walt_WaltUsbConnection_getMaxE()
Dsync_clock.h43 int micros(struct clock_connection *clk);
46 void sync_clocks(struct clock_connection *clk);
49 void update_bounds(struct clock_connection *clk);
/external/grpc-grpc/src/core/lib/gpr/
Dtime_precise.cc29 static void gpr_get_cycle_counter(int64_t int* clk) { in gpr_get_cycle_counter() argument
32 *clk = ret; in gpr_get_cycle_counter()
37 static void gpr_get_cycle_counter(int64_t* clk) { in gpr_get_cycle_counter() argument
40 *clk = (int64_t)(high << 32) | (int64_t)low; in gpr_get_cycle_counter()
61 void gpr_precise_clock_now(gpr_timespec* clk) { in gpr_precise_clock_now() argument
66 clk->clock_type = GPR_CLOCK_PRECISE; in gpr_precise_clock_now()
67 clk->tv_sec = (int64_t)secs; in gpr_precise_clock_now()
68 clk->tv_nsec = (int32_t)(1e9 * (secs - (double)clk->tv_sec)); in gpr_precise_clock_now()
74 void gpr_precise_clock_now(gpr_timespec* clk) { in gpr_precise_clock_now() argument
75 *clk = gpr_now(GPR_CLOCK_REALTIME); in gpr_precise_clock_now()
[all …]
/external/perfetto/src/profiling/common/
Dprofiler_guardrails_unittest.cc34 const auto clk = static_cast<unsigned long>(sysconf(_SC_CLK_TCK)); in TEST() local
48 gc.cpu_guardrail_sec = 5000000 / clk; in TEST()
49 gc.cpu_start_secs = 1000000 / clk; in TEST()
54 const auto clk = static_cast<unsigned long>(sysconf(_SC_CLK_TCK)); in TEST() local
68 gc.cpu_guardrail_sec = 7000000 / clk; in TEST()
69 gc.cpu_start_secs = 1000000 / clk; in TEST()
/external/compiler-rt/lib/tsan/tests/unit/
Dtsan_clock_test.cc24 ThreadClock clk(0); in TEST() local
25 ASSERT_EQ(clk.size(), 1U); in TEST()
26 clk.tick(); in TEST()
27 ASSERT_EQ(clk.size(), 1U); in TEST()
28 ASSERT_EQ(clk.get(0), 1U); in TEST()
29 clk.set(3, clk.get(3) + 1); in TEST()
30 ASSERT_EQ(clk.size(), 4U); in TEST()
31 ASSERT_EQ(clk.get(0), 1U); in TEST()
32 ASSERT_EQ(clk.get(1), 0U); in TEST()
33 ASSERT_EQ(clk.get(2), 0U); in TEST()
[all …]
/external/arm-trusted-firmware/drivers/imx/usdhc/
Dimx_usdhc.c22 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
39 static void imx_usdhc_set_clk(int clk) in imx_usdhc_set_clk() argument
46 assert(clk > 0); in imx_usdhc_set_clk()
48 while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256) in imx_usdhc_set_clk()
51 while (sdhc_clk / div > clk && div < 16) in imx_usdhc_set_clk()
56 clk = (pre_div << 8) | (div << 4); in imx_usdhc_set_clk()
59 mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk); in imx_usdhc_set_clk()
252 static int imx_usdhc_set_ios(unsigned int clk, unsigned int width) in imx_usdhc_set_ios() argument
256 imx_usdhc_set_clk(clk); in imx_usdhc_set_ios()
/external/arm-trusted-firmware/drivers/renesas/rzg/ddr/ddr_b/
Dboot_init_dram_config.c174 void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) in boardcnf_get_brd_clk() argument
181 *clk = 50U; in boardcnf_get_brd_clk()
185 *clk = 60U; in boardcnf_get_brd_clk()
189 *clk = 75U; in boardcnf_get_brd_clk()
193 *clk = 100U; in boardcnf_get_brd_clk()
/external/perfetto/tools/cpu_utilization/
Dcpu_utilization.cc46 uint64_t ReadWallTimeMs(clockid_t clk) { in ReadWallTimeMs() argument
48 PERFETTO_CHECK(clock_gettime(clk, &ts) == 0); in ReadWallTimeMs()
106 auto clk = CLOCK_MONOTONIC_RAW; in CpuUtilizationMain() local
108 PERFETTO_CHECK(clock_getres(clk, &ts) == 0); in CpuUtilizationMain()
127 uint64_t first_walltime_ms = ReadWallTimeMs(clk); in CpuUtilizationMain()
140 uint64_t walltime_ms = ReadWallTimeMs(clk); in CpuUtilizationMain()
/external/llvm-project/compiler-rt/test/sanitizer_common/TestCases/Linux/
Dgetcpuclockid.c7 clockid_t clk; in cpu_ns() local
9 int res = clock_getcpuclockid(getpid(), &clk); in cpu_ns()
11 res = clock_gettime(clk, &ts); in cpu_ns()
/external/perfetto/src/traced/probes/ftrace/test/data/synthetic/
Davailable_events6 clk:clk_enable
7 clk:clk_disable
8 clk:clk_set_rate
/external/rust/crates/grpcio-sys/grpc/src/core/lib/gpr/
Dtime_precise.cc137 void gpr_precise_clock_now(gpr_timespec* clk) { in gpr_precise_clock_now() argument
139 *clk = gpr_cycle_counter_to_time(counter); in gpr_precise_clock_now()
158 void gpr_precise_clock_now(gpr_timespec* clk) { in gpr_precise_clock_now() argument
159 *clk = gpr_now(GPR_CLOCK_REALTIME); in gpr_precise_clock_now()
160 clk->clock_type = GPR_CLOCK_PRECISE; in gpr_precise_clock_now()
/external/llvm-project/compiler-rt/lib/tsan/tests/unit/
Dtsan_clock_test.cpp23 ThreadClock clk(0); in TEST() local
24 ASSERT_EQ(clk.size(), 1U); in TEST()
25 clk.tick(); in TEST()
26 ASSERT_EQ(clk.size(), 1U); in TEST()
27 ASSERT_EQ(clk.get(0), 1U); in TEST()
28 clk.set(&cache, 3, clk.get(3) + 1); in TEST()
29 ASSERT_EQ(clk.size(), 4U); in TEST()
30 ASSERT_EQ(clk.get(0), 1U); in TEST()
31 ASSERT_EQ(clk.get(1), 0U); in TEST()
32 ASSERT_EQ(clk.get(2), 0U); in TEST()
[all …]
/external/arm-trusted-firmware/plat/imx/common/include/sci/svc/pm/
Dsci_pm_api.h454 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
475 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate);
503 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog);
527 sc_pm_clk_t clk, sc_pm_clk_parent_t parent);
548 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent);
/external/arm-trusted-firmware/drivers/renesas/rcar/ddr/ddr_b/
Dboot_init_dram_config.c1539 void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) in boardcnf_get_brd_clk() argument
1544 *clk = 50; in boardcnf_get_brd_clk()
1550 *clk = 50; in boardcnf_get_brd_clk()
1554 *clk = 60; in boardcnf_get_brd_clk()
1558 *clk = 75; in boardcnf_get_brd_clk()
1562 *clk = 100; in boardcnf_get_brd_clk()
/external/perfetto/src/trace_processor/importers/proto/
Dproto_trace_reader.cc363 protos::pbzero::ClockSnapshot::Clock::Decoder clk(*it); in ParseClockSnapshot() local
364 ClockTracker::ClockId clock_id = clk.clock_id(); in ParseClockSnapshot()
365 if (ClockTracker::IsReservedSeqScopedClockId(clk.clock_id())) { in ParseClockSnapshot()
372 clock_id = ClockTracker::SeqScopedClockIdToGlobal(seq_id, clk.clock_id()); in ParseClockSnapshot()
375 clk.unit_multiplier_ns() in ParseClockSnapshot()
376 ? static_cast<int64_t>(clk.unit_multiplier_ns()) in ParseClockSnapshot()
378 clocks.emplace_back(clock_id, clk.timestamp(), unit_multiplier_ns, in ParseClockSnapshot()
379 clk.is_incremental()); in ParseClockSnapshot()
/external/arm-trusted-firmware/plat/imx/common/sci/svc/pm/
Dpm_rpc_clnt.c236 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) in sc_pm_set_clock_rate() argument
246 RPC_U8(&msg, 6U) = (uint8_t)clk; in sc_pm_set_clock_rate()
257 sc_pm_clk_t clk, sc_pm_clock_rate_t *rate) in sc_pm_get_clock_rate() argument
266 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_get_clock_rate()
280 sc_pm_clk_t clk, sc_bool_t enable, sc_bool_t autog) in sc_pm_clock_enable() argument
289 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_clock_enable()
301 sc_pm_clk_t clk, sc_pm_clk_parent_t parent) in sc_pm_set_clock_parent() argument
310 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_set_clock_parent()
321 sc_pm_clk_t clk, sc_pm_clk_parent_t *parent) in sc_pm_get_clock_parent() argument
330 RPC_U8(&msg, 2U) = (uint8_t)clk; in sc_pm_get_clock_parent()
/external/cpuinfo/test/dmesg/
Dgalaxy-grand-prime-value-edition.log53 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [0]ext_26m
54 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [1]ext_32k
55 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [2]clk_mpll
56 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [3]clk_dpll
57 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [4]clk_tdpll
58 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [5]clk_wpll
59 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [6]clk_cpll
60 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [7]clk_wifipll
61 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [8]clk_460m8
62 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [9]clk_300m
[all …]
Dgalaxy-j1-2016.log50 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [0]ext_26m
51 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [1]ext_32k
52 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [2]clk_mpll
53 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [3]clk_dpll
54 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [4]clk_tdpll
55 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [5]clk_wpll
56 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [6]clk_cpll
57 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [7]clk_wifipll
58 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [8]clk_460m8
59 <6>[ 0.000000] [0: swapper/0: 0] [c0] clk: @@@file_clk_data: [9]clk_300m
[all …]
Dmoto-g-gen3.log72 [ 0.420930,1] mdss_mdp_parse_dt_prop_len: prop qcom,mdss-clk-levels : doesn't exist in device tr…
74 [ 0.421270,1] mdss_mdp_irq_clk_register: unable to get clk: lut_clk
509 [ 1.354784,0] clock_late_init: clk xo_clk_src
510 [ 1.354788,0] clock_late_init: clk xo_a_clk_src
511 [ 1.354791,0] clock_late_init: clk xo_otg_clk
512 [ 1.354794,0] clock_late_init: clk xo_lpm_clk
513 [ 1.354797,0] clock_late_init: clk xo_pil_mss_clk
514 [ 1.354801,0] clock_late_init: clk xo_pil_pronto_clk
515 [ 1.354804,0] clock_late_init: clk xo_wlan_clk
516 [ 1.354807,0] clock_late_init: clk snoc_clk
[all …]
/external/arm-trusted-firmware/drivers/rpi3/sdhost/
Drpi3_sdhost.c22 static int rpi3_sdhost_set_ios(unsigned int clk, unsigned int width);
393 static int rpi3_sdhost_set_clock(unsigned int clk) in rpi3_sdhost_set_clock() argument
399 if (clk < 100000) { in rpi3_sdhost_set_clock()
405 div = max_clk / clk; in rpi3_sdhost_set_clock()
409 if ((max_clk / div) > clk) in rpi3_sdhost_set_clock()
425 static int rpi3_sdhost_set_ios(unsigned int clk, unsigned int width) in rpi3_sdhost_set_ios() argument
430 rpi3_sdhost_set_clock(clk); in rpi3_sdhost_set_ios()
431 VERBOSE("rpi3_sdhost: Changing clock to %dHz for data mode\n", clk); in rpi3_sdhost_set_ios()
/external/arm-trusted-firmware/drivers/synopsys/emmc/
Ddw_mmc.c125 static int dw_set_ios(unsigned int clk, unsigned int width);
157 static void dw_set_clk(int clk) in dw_set_clk() argument
162 assert(clk > 0); in dw_set_clk()
165 if ((dw_params.clk_rate / (2 * div)) <= clk) { in dw_set_clk()
322 static int dw_set_ios(unsigned int clk, unsigned int width) in dw_set_ios() argument
338 dw_set_clk(clk); in dw_set_ios()
/external/arm-trusted-firmware/plat/intel/soc/common/include/
Dsocfpga_private.h14 #define EMMC_INIT_PARAMS(base, clk) \ argument
16 .clk_rate = (clk), \

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