/external/llvm-project/llvm/test/CodeGen/Mips/ |
D | dsp-patterns-cmp-vselect.ll | 7 define { i32 } @select_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { 9 %0 = bitcast i32 %a0.coerce to <2 x i16> 10 %1 = bitcast i32 %a1.coerce to <2 x i16> 11 %2 = bitcast i32 %a2.coerce to <2 x i16> 12 %3 = bitcast i32 %a3.coerce to <2 x i16> 24 define { i32 } @select_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { 26 %0 = bitcast i32 %a0.coerce to <2 x i16> 27 %1 = bitcast i32 %a1.coerce to <2 x i16> 28 %2 = bitcast i32 %a2.coerce to <2 x i16> 29 %3 = bitcast i32 %a3.coerce to <2 x i16> [all …]
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D | dsp-r2.ll | 3 define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nou… 7 %1 = bitcast i32 %a1.coerce to <2 x i16> 8 %2 = bitcast i32 %a2.coerce to <2 x i16> 15 define i64 @test__builtin_mips_dps_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nou… 19 %1 = bitcast i32 %a1.coerce to <2 x i16> 20 %2 = bitcast i32 %a2.coerce to <2 x i16> 27 define i64 @test__builtin_mips_mulsa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… 31 %1 = bitcast i32 %a1.coerce to <2 x i16> 32 %2 = bitcast i32 %a2.coerce to <2 x i16> 39 define i64 @test__builtin_mips_dpax_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) no… [all …]
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D | dsp-r1.ll | 112 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… 116 %1 = bitcast i32 %a1.coerce to <4 x i8> 117 %2 = bitcast i32 %a2.coerce to <4 x i8> 124 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… 128 %1 = bitcast i32 %a1.coerce to <4 x i8> 129 %2 = bitcast i32 %a2.coerce to <4 x i8> 136 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… 140 %1 = bitcast i32 %a1.coerce to <4 x i8> 141 %2 = bitcast i32 %a2.coerce to <4 x i8> 148 define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… [all …]
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D | dsp-patterns.ll | 37 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) { 39 %0 = bitcast i32 %a.coerce to <2 x i16> 40 %1 = bitcast i32 %b.coerce to <2 x i16> 50 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) { 52 %0 = bitcast i32 %a.coerce to <2 x i16> 53 %1 = bitcast i32 %b.coerce to <2 x i16> 68 define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) { 70 %0 = bitcast i32 %a.coerce to <2 x i16> 71 %1 = bitcast i32 %b.coerce to <2 x i16> 81 define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) { [all …]
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/external/llvm/test/CodeGen/Mips/ |
D | dsp-patterns-cmp-vselect.ll | 7 define { i32 } @select_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { 9 %0 = bitcast i32 %a0.coerce to <2 x i16> 10 %1 = bitcast i32 %a1.coerce to <2 x i16> 11 %2 = bitcast i32 %a2.coerce to <2 x i16> 12 %3 = bitcast i32 %a3.coerce to <2 x i16> 24 define { i32 } @select_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { 26 %0 = bitcast i32 %a0.coerce to <2 x i16> 27 %1 = bitcast i32 %a1.coerce to <2 x i16> 28 %2 = bitcast i32 %a2.coerce to <2 x i16> 29 %3 = bitcast i32 %a3.coerce to <2 x i16> [all …]
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D | dsp-r2.ll | 3 define i64 @test__builtin_mips_dpa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nou… 7 %1 = bitcast i32 %a1.coerce to <2 x i16> 8 %2 = bitcast i32 %a2.coerce to <2 x i16> 15 define i64 @test__builtin_mips_dps_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) nou… 19 %1 = bitcast i32 %a1.coerce to <2 x i16> 20 %2 = bitcast i32 %a2.coerce to <2 x i16> 27 define i64 @test__builtin_mips_mulsa_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… 31 %1 = bitcast i32 %a1.coerce to <2 x i16> 32 %2 = bitcast i32 %a2.coerce to <2 x i16> 39 define i64 @test__builtin_mips_dpax_w_ph1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) no… [all …]
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D | dsp-r1.ll | 112 define i64 @test__builtin_mips_dpau_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… 116 %1 = bitcast i32 %a1.coerce to <4 x i8> 117 %2 = bitcast i32 %a2.coerce to <4 x i8> 124 define i64 @test__builtin_mips_dpau_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… 128 %1 = bitcast i32 %a1.coerce to <4 x i8> 129 %2 = bitcast i32 %a2.coerce to <4 x i8> 136 define i64 @test__builtin_mips_dpsu_h_qbl1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… 140 %1 = bitcast i32 %a1.coerce to <4 x i8> 141 %2 = bitcast i32 %a2.coerce to <4 x i8> 148 define i64 @test__builtin_mips_dpsu_h_qbr1(i32 %i0, i32, i64 %a0, i32 %a1.coerce, i32 %a2.coerce) n… [all …]
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D | dsp-patterns.ll | 37 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) { 39 %0 = bitcast i32 %a.coerce to <2 x i16> 40 %1 = bitcast i32 %b.coerce to <2 x i16> 50 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) { 52 %0 = bitcast i32 %a.coerce to <2 x i16> 53 %1 = bitcast i32 %b.coerce to <2 x i16> 68 define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) { 70 %0 = bitcast i32 %a.coerce to <2 x i16> 71 %1 = bitcast i32 %b.coerce to <2 x i16> 81 define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) { [all …]
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/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/ |
D | vld24.ll | 81 define arm_aapcs_vfpcc void @test_vst2q_u32(i32* %addr, %struct.uint32x4x2_t %value.coerce) { 90 %value.coerce.fca.0.0.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 0 91 %value.coerce.fca.0.1.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 1 92 …m.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coer… 93 …m.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coer… 97 define arm_aapcs_vfpcc i32* @test_vst2q_u32_post(i32* %addr, %struct.uint32x4x2_t %value.coerce) { 106 %value.coerce.fca.0.0.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 0 107 %value.coerce.fca.0.1.extract = extractvalue %struct.uint32x4x2_t %value.coerce, 0, 1 108 …m.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coer… 109 …m.mve.vst2q.p0i32.v4i32(i32* %addr, <4 x i32> %value.coerce.fca.0.0.extract, <4 x i32> %value.coer… [all …]
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/external/llvm/test/Transforms/LoopRotate/ |
D | nosimplifylatch.ll | 9 …St3__14findINS_11__wrap_iterIPiEEiEET_S4_S4_RKT0_(i64 %__first.coerce, i64 %__last.coerce, i32* no… 11 %coerce.val.ip = inttoptr i64 %__first.coerce to i32* 12 %coerce.val.ip2 = inttoptr i64 %__last.coerce to i32* 16 %coerce.val.ip9 = phi i32* [ %incdec.ptr.i, %for.inc ], [ %coerce.val.ip, %entry ] 17 %lnot.i = icmp eq i32* %coerce.val.ip9, %coerce.val.ip2 21 %0 = load i32, i32* %coerce.val.ip9, align 4 27 %incdec.ptr.i = getelementptr inbounds i32, i32* %coerce.val.ip9, i64 1 31 %coerce.val.ip9.lcssa = phi i32* [ %coerce.val.ip9, %for.cond ], [ %coerce.val.ip9, %for.body ] 32 %coerce.val.pi = ptrtoint i32* %coerce.val.ip9.lcssa to i64 33 ret i64 %coerce.val.pi
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/external/llvm-project/llvm/test/Transforms/LoopRotate/ |
D | nosimplifylatch.ll | 9 …St3__14findINS_11__wrap_iterIPiEEiEET_S4_S4_RKT0_(i64 %__first.coerce, i64 %__last.coerce, i32* no… 11 %coerce.val.ip = inttoptr i64 %__first.coerce to i32* 12 %coerce.val.ip2 = inttoptr i64 %__last.coerce to i32* 16 %coerce.val.ip9 = phi i32* [ %incdec.ptr.i, %for.inc ], [ %coerce.val.ip, %entry ] 17 %lnot.i = icmp eq i32* %coerce.val.ip9, %coerce.val.ip2 21 %0 = load i32, i32* %coerce.val.ip9, align 4 27 %incdec.ptr.i = getelementptr inbounds i32, i32* %coerce.val.ip9, i64 1 31 %coerce.val.ip9.lcssa = phi i32* [ %coerce.val.ip9, %for.cond ], [ %coerce.val.ip9, %for.body ] 32 %coerce.val.pi = ptrtoint i32* %coerce.val.ip9.lcssa to i64 33 ret i64 %coerce.val.pi
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/external/llvm/test/Transforms/SLPVectorizer/ARM/ |
D | sroa.ll | 15 …Aed(%class.Complex* noalias nocapture sret %agg.result, [4 x i32] %a.coerce, [4 x i32] %b.coerce) { 17 %a.coerce.fca.0.extract = extractvalue [4 x i32] %a.coerce, 0 18 %a.sroa.0.0.insert.ext = zext i32 %a.coerce.fca.0.extract to i64 19 %a.coerce.fca.1.extract = extractvalue [4 x i32] %a.coerce, 1 20 %a.sroa.0.4.insert.ext = zext i32 %a.coerce.fca.1.extract to i64 24 %a.coerce.fca.2.extract = extractvalue [4 x i32] %a.coerce, 2 25 %a.sroa.3.8.insert.ext = zext i32 %a.coerce.fca.2.extract to i64 26 %a.coerce.fca.3.extract = extractvalue [4 x i32] %a.coerce, 3 27 %a.sroa.3.12.insert.ext = zext i32 %a.coerce.fca.3.extract to i64 31 %b.coerce.fca.0.extract = extractvalue [4 x i32] %b.coerce, 0 [all …]
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/external/llvm-project/llvm/test/CodeGen/AArch64/ |
D | aarch64-bf16-ldst-intrinsics.ll | 226 define %struct.bfloat16x4x2_t @test_vld2_lane_bf16(bfloat* %ptr, [2 x <4 x bfloat>] %src.coerce) lo… 232 %src.coerce.fca.0.extract = extractvalue [2 x <4 x bfloat>] %src.coerce, 0 233 %src.coerce.fca.1.extract = extractvalue [2 x <4 x bfloat>] %src.coerce, 1 235 …m.aarch64.neon.ld2lane.v4bf16.p0i8(<4 x bfloat> %src.coerce.fca.0.extract, <4 x bfloat> %src.coerc… 246 define %struct.bfloat16x8x2_t @test_vld2q_lane_bf16(bfloat* %ptr, [2 x <8 x bfloat>] %src.coerce) l… 252 %src.coerce.fca.0.extract = extractvalue [2 x <8 x bfloat>] %src.coerce, 0 253 %src.coerce.fca.1.extract = extractvalue [2 x <8 x bfloat>] %src.coerce, 1 255 …m.aarch64.neon.ld2lane.v8bf16.p0i8(<8 x bfloat> %src.coerce.fca.0.extract, <8 x bfloat> %src.coerc… 306 define %struct.bfloat16x4x3_t @test_vld3_lane_bf16(bfloat* %ptr, [3 x <4 x bfloat>] %src.coerce) lo… 312 %src.coerce.fca.0.extract = extractvalue [3 x <4 x bfloat>] %src.coerce, 0 [all …]
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/external/llvm-project/llvm/test/CodeGen/ARM/ |
D | bf16-intrinsics-ld-st.ll | 224 …e arm_aapcs_vfpcc [2 x <2 x i32>] @test_vld2_lane_bf16(bfloat* %ptr, [2 x <2 x i32>] %src.coerce) { 232 %src.coerce.fca.0.extract = extractvalue [2 x <2 x i32>] %src.coerce, 0 233 %src.coerce.fca.1.extract = extractvalue [2 x <2 x i32>] %src.coerce, 1 234 %0 = bitcast <2 x i32> %src.coerce.fca.0.extract to <4 x bfloat> 235 %1 = bitcast <2 x i32> %src.coerce.fca.1.extract to <4 x bfloat> 247 … arm_aapcs_vfpcc [2 x <4 x i32>] @test_vld2q_lane_bf16(bfloat* %ptr, [2 x <4 x i32>] %src.coerce) { 255 %src.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %src.coerce, 0 256 %src.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %src.coerce, 1 257 %0 = bitcast <4 x i32> %src.coerce.fca.0.extract to <8 x bfloat> 258 %1 = bitcast <4 x i32> %src.coerce.fca.1.extract to <8 x bfloat> [all …]
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D | fp16-instructions.ll | 34 ; that for the time being by passing "float %f.coerce" and the necessary 38 define float @RetValBug(float %A.coerce) { 49 define float @Add(float %a.coerce, float %b.coerce) { 51 %0 = bitcast float %a.coerce to i32 54 %2 = bitcast float %b.coerce to i32 105 define zeroext i1 @VCMP1(float %F.coerce, float %G.coerce) { 107 %0 = bitcast float %F.coerce to i32 110 %2 = bitcast float %G.coerce to i32 138 define zeroext i1 @VCMP2(float %F.coerce) { 140 %0 = bitcast float %F.coerce to i32 [all …]
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/external/llvm-project/llvm/test/Transforms/SLPVectorizer/ARM/ |
D | sroa.ll | 12 …ex* noalias nocapture sret(%class.Complex) %agg.result, [4 x i32] %a.coerce, [4 x i32] %b.coerce) { 52 %a.coerce.fca.0.extract = extractvalue [4 x i32] %a.coerce, 0 53 %a.sroa.0.0.insert.ext = zext i32 %a.coerce.fca.0.extract to i64 54 %a.coerce.fca.1.extract = extractvalue [4 x i32] %a.coerce, 1 55 %a.sroa.0.4.insert.ext = zext i32 %a.coerce.fca.1.extract to i64 59 %a.coerce.fca.2.extract = extractvalue [4 x i32] %a.coerce, 2 60 %a.sroa.3.8.insert.ext = zext i32 %a.coerce.fca.2.extract to i64 61 %a.coerce.fca.3.extract = extractvalue [4 x i32] %a.coerce, 3 62 %a.sroa.3.12.insert.ext = zext i32 %a.coerce.fca.3.extract to i64 66 %b.coerce.fca.0.extract = extractvalue [4 x i32] %b.coerce, 0 [all …]
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/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
D | irtranslator-duplicate-types-param.ll | 9 define i64 @param_two_struct([2 x i64] %t.coerce, [2 x i64] %s.coerce) { 11 %t.coerce.fca.0.extract = extractvalue [2 x i64] %t.coerce, 0 12 %s.coerce.fca.1.extract = extractvalue [2 x i64] %s.coerce, 1 13 %add = add nsw i64 %s.coerce.fca.1.extract, %t.coerce.fca.0.extract
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/external/llvm-project/llvm/test/Transforms/EarlyCSE/AArch64/ |
D | intrinsics.ll | 6 define <4 x i32> @test_cse(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) { 11 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0 12 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1 23 %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8> 24 %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8> 40 define <4 x i32> @test_cse2(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) { 45 …all void @llvm.aarch64.neon.st2.v4i32.p0i8(<4 x i32> %s.coerce.fca.0.extract, <4 x i32> %s.coerce.… 46 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0 47 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1 58 %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8> [all …]
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/external/llvm/test/Transforms/EarlyCSE/AArch64/ |
D | intrinsics.ll | 4 define <4 x i32> @test_cse(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) { 9 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0 10 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1 21 %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8> 22 %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8> 38 define <4 x i32> @test_cse2(i32* %a, [2 x <4 x i32>] %s.coerce, i32 %n) { 44 %s.coerce.fca.0.extract = extractvalue [2 x <4 x i32>] %s.coerce, 0 45 %s.coerce.fca.1.extract = extractvalue [2 x <4 x i32>] %s.coerce, 1 56 %1 = bitcast <4 x i32> %s.coerce.fca.0.extract to <16 x i8> 57 %2 = bitcast <4 x i32> %s.coerce.fca.1.extract to <16 x i8> [all …]
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/external/llvm-project/llvm/test/Transforms/InstCombine/ |
D | vector-type.ll | 6 define i32 @vselect1(i32 %a.coerce, i32 %b.coerce, i32 %c.coerce) { 8 %0 = bitcast i32 %a.coerce to <2 x i16> 9 %1 = bitcast i32 %b.coerce to <2 x i16> 10 %2 = bitcast i32 %c.coerce to <2 x i16>
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/external/llvm/test/Transforms/InstCombine/ |
D | vector-type.ll | 6 define i32 @vselect1(i32 %a.coerce, i32 %b.coerce, i32 %c.coerce) { 8 %0 = bitcast i32 %a.coerce to <2 x i16> 9 %1 = bitcast i32 %b.coerce to <2 x i16> 10 %2 = bitcast i32 %c.coerce to <2 x i16>
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/external/llvm-project/llvm/test/CodeGen/PowerPC/ |
D | varargs-struct-float.ll | 8 define void @foo(float inreg %s.coerce) nounwind { 11 %coerce.dive = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0 12 store float %s.coerce, float* %coerce.dive, align 1 13 %coerce.dive1 = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0 14 %0 = load float, float* %coerce.dive1, align 1
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D | f128-aggregates.ll | 75 define fp128 @testStruct_01(fp128 inreg returned %a.coerce) { 89 ret fp128 %a.coerce 93 define fp128 @testStruct_02([8 x fp128] %a.coerce) { 111 %a.coerce.fca.7.extract = extractvalue [8 x fp128] %a.coerce, 7 112 ret fp128 %a.coerce.fca.7.extract 169 define fp128 @testStruct_04([8 x fp128] %a.coerce) { 187 %a.coerce.fca.3.extract = extractvalue [8 x fp128] %a.coerce, 3 188 ret fp128 %a.coerce.fca.3.extract 192 define fp128 @testHUnion_01([1 x fp128] %a.coerce) { 206 %a.coerce.fca.0.extract = extractvalue [1 x fp128] %a.coerce, 0 [all …]
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/external/llvm/test/CodeGen/PowerPC/ |
D | varargs-struct-float.ll | 8 define void @foo(float inreg %s.coerce) nounwind { 11 %coerce.dive = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0 12 store float %s.coerce, float* %coerce.dive, align 1 13 %coerce.dive1 = getelementptr %struct.Sf1, %struct.Sf1* %s, i32 0, i32 0 14 %0 = load float, float* %coerce.dive1, align 1
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/external/llvm-project/llvm/test/CodeGen/X86/GlobalISel/ |
D | x86_64-irtranslator-struct-return.ll | 12 define float @test_return_f1(float %f.coerce) { 21 ; ALL: G_STORE [[TRUNC]](s32), [[FRAME_INDEX1]](p0) :: (store 4 into %ir.coerce.dive2) 23 …AD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load 4 from %ir.coerce.dive13) 30 %coerce.dive = getelementptr inbounds %struct.f1, %struct.f1* %f, i32 0, i32 0 31 store float %f.coerce, float* %coerce.dive, align 4 35 %coerce.dive1 = getelementptr inbounds %struct.f1, %struct.f1* %retval, i32 0, i32 0 36 %2 = load float, float* %coerce.dive1, align 4 42 define double @test_return_d1(double %d.coerce) { 51 ; ALL: G_STORE [[TRUNC]](s64), [[FRAME_INDEX1]](p0) :: (store 8 into %ir.coerce.dive2) 53 …AD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (dereferenceable load 8 from %ir.coerce.dive13) [all …]
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