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1 /**********************************************************
2  * Copyright 1998-2015 VMware, Inc.  All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person
5  * obtaining a copy of this software and associated documentation
6  * files (the "Software"), to deal in the Software without
7  * restriction, including without limitation the rights to use, copy,
8  * modify, merge, publish, distribute, sublicense, and/or sell copies
9  * of the Software, and to permit persons to whom the Software is
10  * furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be
13  * included in all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  *
24  **********************************************************/
25 
26 /*
27  * svga_reg.h --
28  *
29  *    Virtual hardware definitions for the VMware SVGA II device.
30  */
31 
32 #ifndef _SVGA_REG_H_
33 #define _SVGA_REG_H_
34 
35 #include "svga_types.h"
36 
37 /*
38  * SVGA_REG_ENABLE bit definitions.
39  */
40 typedef enum {
41    SVGA_REG_ENABLE_DISABLE = 0,
42    SVGA_REG_ENABLE_ENABLE = (1 << 0),
43    SVGA_REG_ENABLE_HIDE = (1 << 1),
44 } SvgaRegEnable;
45 
46 typedef uint32 SVGAMobId;
47 
48 /*
49  * Arbitrary and meaningless limits. Please ignore these when writing
50  * new drivers.
51  */
52 #define SVGA_MAX_WIDTH                  2560
53 #define SVGA_MAX_HEIGHT                 1600
54 #define SVGA_MAX_BITS_PER_PIXEL         32
55 #define SVGA_MAX_DEPTH                  24
56 #define SVGA_MAX_DISPLAYS               10
57 
58 /*
59  * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
60  * cursor bypass mode. This is still supported, but no new guest
61  * drivers should use it.
62  */
63 #define SVGA_CURSOR_ON_HIDE            0x0   /* Must be 0 to maintain backward compatibility */
64 #define SVGA_CURSOR_ON_SHOW            0x1   /* Must be 1 to maintain backward compatibility */
65 #define SVGA_CURSOR_ON_REMOVE_FROM_FB  0x2   /* Remove the cursor from the framebuffer because we need to see what's under it */
66 #define SVGA_CURSOR_ON_RESTORE_TO_FB   0x3   /* Put the cursor back in the framebuffer so the user can see it */
67 
68 /*
69  * The maximum framebuffer size that can traced for e.g. guests in VESA mode.
70  * The changeMap in the monitor is proportional to this number. Therefore, we'd
71  * like to keep it as small as possible to reduce monitor overhead (using
72  * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over
73  * 4k!).
74  *
75  * NB: For compatibility reasons, this value must be greater than 0xff0000.
76  *     See bug 335072.
77  */
78 #define SVGA_FB_MAX_TRACEABLE_SIZE      0x1000000
79 
80 #define SVGA_MAX_PSEUDOCOLOR_DEPTH      8
81 #define SVGA_MAX_PSEUDOCOLORS           (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
82 #define SVGA_NUM_PALETTE_REGS           (3 * SVGA_MAX_PSEUDOCOLORS)
83 
84 #define SVGA_MAGIC         0x900000UL
85 #define SVGA_MAKE_ID(ver)  (SVGA_MAGIC << 8 | (ver))
86 
87 /* Version 2 let the address of the frame buffer be unsigned on Win32 */
88 #define SVGA_VERSION_2     2
89 #define SVGA_ID_2          SVGA_MAKE_ID(SVGA_VERSION_2)
90 
91 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
92    PALETTE_BASE has moved */
93 #define SVGA_VERSION_1     1
94 #define SVGA_ID_1          SVGA_MAKE_ID(SVGA_VERSION_1)
95 
96 /* Version 0 is the initial version */
97 #define SVGA_VERSION_0     0
98 #define SVGA_ID_0          SVGA_MAKE_ID(SVGA_VERSION_0)
99 
100 /* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */
101 #define SVGA_ID_INVALID    0xFFFFFFFF
102 
103 /* Port offsets, relative to BAR0 */
104 #define SVGA_INDEX_PORT         0x0
105 #define SVGA_VALUE_PORT         0x1
106 #define SVGA_BIOS_PORT          0x2
107 #define SVGA_IRQSTATUS_PORT     0x8
108 
109 /*
110  * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
111  *
112  * Interrupts are only supported when the
113  * SVGA_CAP_IRQMASK capability is present.
114  */
115 #define SVGA_IRQFLAG_ANY_FENCE            0x1    /* Any fence was passed */
116 #define SVGA_IRQFLAG_FIFO_PROGRESS        0x2    /* Made forward progress in the FIFO */
117 #define SVGA_IRQFLAG_FENCE_GOAL           0x4    /* SVGA_FIFO_FENCE_GOAL reached */
118 #define SVGA_IRQFLAG_COMMAND_BUFFER       0x8    /* Command buffer completed */
119 #define SVGA_IRQFLAG_ERROR                0x10   /* Error while processing commands */
120 
121 /*
122  * Registers
123  */
124 
125 enum {
126    SVGA_REG_ID = 0,
127    SVGA_REG_ENABLE = 1,
128    SVGA_REG_WIDTH = 2,
129    SVGA_REG_HEIGHT = 3,
130    SVGA_REG_MAX_WIDTH = 4,
131    SVGA_REG_MAX_HEIGHT = 5,
132    SVGA_REG_DEPTH = 6,
133    SVGA_REG_BITS_PER_PIXEL = 7,       /* Current bpp in the guest */
134    SVGA_REG_PSEUDOCOLOR = 8,
135    SVGA_REG_RED_MASK = 9,
136    SVGA_REG_GREEN_MASK = 10,
137    SVGA_REG_BLUE_MASK = 11,
138    SVGA_REG_BYTES_PER_LINE = 12,
139    SVGA_REG_FB_START = 13,            /* (Deprecated) */
140    SVGA_REG_FB_OFFSET = 14,
141    SVGA_REG_VRAM_SIZE = 15,
142    SVGA_REG_FB_SIZE = 16,
143 
144    /* ID 0 implementation only had the above registers, then the palette */
145    SVGA_REG_ID_0_TOP = 17,
146 
147    SVGA_REG_CAPABILITIES = 17,
148    SVGA_REG_MEM_START = 18,           /* (Deprecated) */
149    SVGA_REG_MEM_SIZE = 19,
150    SVGA_REG_CONFIG_DONE = 20,         /* Set when memory area configured */
151    SVGA_REG_SYNC = 21,                /* See "FIFO Synchronization Registers" */
152    SVGA_REG_BUSY = 22,                /* See "FIFO Synchronization Registers" */
153    SVGA_REG_GUEST_ID = 23,            /* Set guest OS identifier */
154    SVGA_REG_CURSOR_ID = 24,           /* (Deprecated) */
155    SVGA_REG_CURSOR_X = 25,            /* (Deprecated) */
156    SVGA_REG_CURSOR_Y = 26,            /* (Deprecated) */
157    SVGA_REG_CURSOR_ON = 27,           /* (Deprecated) */
158    SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
159    SVGA_REG_SCRATCH_SIZE = 29,        /* Number of scratch registers */
160    SVGA_REG_MEM_REGS = 30,            /* Number of FIFO registers */
161    SVGA_REG_NUM_DISPLAYS = 31,        /* (Deprecated) */
162    SVGA_REG_PITCHLOCK = 32,           /* Fixed pitch for all modes */
163    SVGA_REG_IRQMASK = 33,             /* Interrupt mask */
164 
165    /* Legacy multi-monitor support */
166    SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
167    SVGA_REG_DISPLAY_ID = 35,        /* Display ID for the following display attributes */
168    SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
169    SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
170    SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
171    SVGA_REG_DISPLAY_WIDTH = 39,     /* The display's width */
172    SVGA_REG_DISPLAY_HEIGHT = 40,    /* The display's height */
173 
174    /* See "Guest memory regions" below. */
175    SVGA_REG_GMR_ID = 41,
176    SVGA_REG_GMR_DESCRIPTOR = 42,
177    SVGA_REG_GMR_MAX_IDS = 43,
178    SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
179 
180    SVGA_REG_TRACES = 45,            /* Enable trace-based updates even when FIFO is on */
181    SVGA_REG_GMRS_MAX_PAGES = 46,    /* Maximum number of 4KB pages for all GMRs */
182    SVGA_REG_MEMORY_SIZE = 47,       /* Total dedicated device memory excluding FIFO */
183    SVGA_REG_COMMAND_LOW = 48,       /* Lower 32 bits and submits commands */
184    SVGA_REG_COMMAND_HIGH = 49,      /* Upper 32 bits of command buffer PA */
185    SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50,   /* Max primary memory */
186    SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Suggested limit on mob mem */
187    SVGA_REG_DEV_CAP = 52,           /* Write dev cap index, read value */
188    SVGA_REG_CMD_PREPEND_LOW = 53,
189    SVGA_REG_iCMD_PREPEND_HIGH = 54,
190    SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
191    SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
192    SVGA_REG_MOB_MAX_SIZE = 57,
193    SVGA_REG_BLANK_SCREEN_TARGETS = 58,
194    SVGA_REG_CAP2 = 59,
195    SVGA_REG_TOP = 60,               /* Must be 1 more than the last register */
196 
197    SVGA_PALETTE_BASE = 1024,        /* Base of SVGA color map */
198    /* Next 768 (== 256*3) registers exist for colormap */
199    SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
200                                     /* Base of scratch registers */
201    /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
202       First 4 are reserved for VESA BIOS Extension; any remaining are for
203       the use of the current SVGA driver. */
204 };
205 
206 /*
207  * Guest memory regions (GMRs):
208  *
209  * This is a new memory mapping feature available in SVGA devices
210  * which have the SVGA_CAP_GMR bit set. Previously, there were two
211  * fixed memory regions available with which to share data between the
212  * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
213  * are our name for an extensible way of providing arbitrary DMA
214  * buffers for use between the driver and the SVGA device. They are a
215  * new alternative to framebuffer memory, usable for both 2D and 3D
216  * graphics operations.
217  *
218  * Since GMR mapping must be done synchronously with guest CPU
219  * execution, we use a new pair of SVGA registers:
220  *
221  *   SVGA_REG_GMR_ID --
222  *
223  *     Read/write.
224  *     This register holds the 32-bit ID (a small positive integer)
225  *     of a GMR to create, delete, or redefine. Writing this register
226  *     has no side-effects.
227  *
228  *   SVGA_REG_GMR_DESCRIPTOR --
229  *
230  *     Write-only.
231  *     Writing this register will create, delete, or redefine the GMR
232  *     specified by the above ID register. If this register is zero,
233  *     the GMR is deleted. Any pointers into this GMR (including those
234  *     currently being processed by FIFO commands) will be
235  *     synchronously invalidated.
236  *
237  *     If this register is nonzero, it must be the physical page
238  *     number (PPN) of a data structure which describes the physical
239  *     layout of the memory region this GMR should describe. The
240  *     descriptor structure will be read synchronously by the SVGA
241  *     device when this register is written. The descriptor need not
242  *     remain allocated for the lifetime of the GMR.
243  *
244  *     The guest driver should write SVGA_REG_GMR_ID first, then
245  *     SVGA_REG_GMR_DESCRIPTOR.
246  *
247  *   SVGA_REG_GMR_MAX_IDS --
248  *
249  *     Read-only.
250  *     The SVGA device may choose to support a maximum number of
251  *     user-defined GMR IDs. This register holds the number of supported
252  *     IDs. (The maximum supported ID plus 1)
253  *
254  *   SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
255  *
256  *     Read-only.
257  *     The SVGA device may choose to put a limit on the total number
258  *     of SVGAGuestMemDescriptor structures it will read when defining
259  *     a single GMR.
260  *
261  * The descriptor structure is an array of SVGAGuestMemDescriptor
262  * structures. Each structure may do one of three things:
263  *
264  *   - Terminate the GMR descriptor list.
265  *     (ppn==0, numPages==0)
266  *
267  *   - Add a PPN or range of PPNs to the GMR's virtual address space.
268  *     (ppn != 0, numPages != 0)
269  *
270  *   - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
271  *     support multi-page GMR descriptor tables without forcing the
272  *     driver to allocate physically contiguous memory.
273  *     (ppn != 0, numPages == 0)
274  *
275  * Note that each physical page of SVGAGuestMemDescriptor structures
276  * can describe at least 2MB of guest memory. If the driver needs to
277  * use more than one page of descriptor structures, it must use one of
278  * its SVGAGuestMemDescriptors to point to an additional page.  The
279  * device will never automatically cross a page boundary.
280  *
281  * Once the driver has described a GMR, it is immediately available
282  * for use via any FIFO command that uses an SVGAGuestPtr structure.
283  * These pointers include a GMR identifier plus an offset into that
284  * GMR.
285  *
286  * The driver must check the SVGA_CAP_GMR bit before using the GMR
287  * registers.
288  */
289 
290 /*
291  * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
292  * memory as well.  In the future, these IDs could even be used to
293  * allow legacy memory regions to be redefined by the guest as GMRs.
294  *
295  * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
296  * is being phased out. Please try to use user-defined GMRs whenever
297  * possible.
298  */
299 #define SVGA_GMR_NULL         ((uint32) -1)
300 #define SVGA_GMR_FRAMEBUFFER  ((uint32) -2)  // Guest Framebuffer (GFB)
301 
302 typedef
303 struct SVGAGuestMemDescriptor {
304    uint32 ppn;
305    uint32 numPages;
306 } SVGAGuestMemDescriptor;
307 
308 typedef
309 struct SVGAGuestPtr {
310    uint32 gmrId;
311    uint32 offset;
312 } SVGAGuestPtr;
313 
314 /*
315  * Register based command buffers --
316  *
317  * Provide an SVGA device interface that allows the guest to submit
318  * command buffers to the SVGA device through an SVGA device register.
319  * The metadata for each command buffer is contained in the
320  * SVGACBHeader structure along with the return status codes.
321  *
322  * The SVGA device supports command buffers if
323  * SVGA_CAP_COMMAND_BUFFERS is set in the device caps register.  The
324  * fifo must be enabled for command buffers to be submitted.
325  *
326  * Command buffers are submitted when the guest writing the 64 byte
327  * aligned physical address into the SVGA_REG_COMMAND_LOW and
328  * SVGA_REG_COMMAND_HIGH.  SVGA_REG_COMMAND_HIGH contains the upper 32
329  * bits of the physical address.  SVGA_REG_COMMAND_LOW contains the
330  * lower 32 bits of the physical address, since the command buffer
331  * headers are required to be 64 byte aligned the lower 6 bits are
332  * used for the SVGACBContext value.  Writing to SVGA_REG_COMMAND_LOW
333  * submits the command buffer to the device and queues it for
334  * execution.  The SVGA device supports at least
335  * SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued
336  * per context and if that limit is reached the device will write the
337  * status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command
338  * buffer header synchronously and not raise any IRQs.
339  *
340  * It is invalid to submit a command buffer without a valid physical
341  * address and results are undefined.
342  *
343  * The device guarantees that command buffers of size SVGA_CB_MAX_SIZE
344  * will be supported.  If a larger command buffer is submitted results
345  * are unspecified and the device will either complete the command
346  * buffer or return an error.
347  *
348  * The device guarantees that any individual command in a command
349  * buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is
350  * enough to fit a 64x64 color-cursor definition.  If the command is
351  * too large the device is allowed to process the command or return an
352  * error.
353  *
354  * The device context is a special SVGACBContext that allows for
355  * synchronous register like accesses with the flexibility of
356  * commands.  There is a different command set defined by
357  * SVGADeviceContextCmdId.  The commands in each command buffer is not
358  * allowed to straddle physical pages.
359  */
360 
361 #define SVGA_CB_MAX_SIZE (512 * 1024)  // 512 KB
362 #define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
363 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB
364 
365 #define SVGA_CB_CONTEXT_MASK 0x3f
366 typedef enum {
367    SVGA_CB_CONTEXT_DEVICE = 0x3f,
368    SVGA_CB_CONTEXT_0      = 0x0,
369    SVGA_CB_CONTEXT_MAX    = 0x1,
370 } SVGACBContext;
371 
372 
373 typedef enum {
374    /*
375     * The guest is supposed to write SVGA_CB_STATUS_NONE to the status
376     * field before submitting the command buffer header, the host will
377     * change the value when it is done with the command buffer.
378     */
379    SVGA_CB_STATUS_NONE             = 0,
380 
381    /*
382     * Written by the host when a command buffer completes successfully.
383     * The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless
384     * the SVGA_CB_FLAG_NO_IRQ flag is set.
385     */
386    SVGA_CB_STATUS_COMPLETED        = 1,
387 
388    /*
389     * Written by the host synchronously with the command buffer
390     * submission to indicate the command buffer was not submitted.  No
391     * IRQ is raised.
392     */
393    SVGA_CB_STATUS_QUEUE_FULL       = 2,
394 
395    /*
396     * Written by the host when an error was detected parsing a command
397     * in the command buffer, errorOffset is written to contain the
398     * offset to the first byte of the failing command.  The device
399     * raises the IRQ with both SVGA_IRQFLAG_ERROR and
400     * SVGA_IRQFLAG_COMMAND_BUFFER.  Some of the commands may have been
401     * processed.
402     */
403    SVGA_CB_STATUS_COMMAND_ERROR    = 3,
404 
405    /*
406     * Written by the host if there is an error parsing the command
407     * buffer header.  The device raises the IRQ with both
408     * SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER.  The device
409     * did not processes any of the command buffer.
410     */
411    SVGA_CB_STATUS_CB_HEADER_ERROR  = 4,
412 
413    /*
414     * Written by the host if the guest requested the host to preempt
415     * the command buffer.  The device will not raise any IRQs and the
416     * command buffer was not processed.
417     */
418    SVGA_CB_STATUS_PREEMPTED        = 5,
419 } SVGACBStatus;
420 
421 typedef enum {
422    SVGA_CB_FLAG_NONE     = 0,
423    SVGA_CB_FLAG_NO_IRQ   = 1 << 0,
424 } SVGACBFlags;
425 
426 typedef
427 struct {
428    volatile SVGACBStatus status;
429    volatile uint32 errorOffset;
430    uint64 id;
431    SVGACBFlags flags;
432    uint32 length;
433    union {
434       PA pa;
435    } ptr;
436    uint32 mustBeZero[8];
437 } SVGACBHeader;
438 
439 typedef enum {
440    SVGA_DC_CMD_NOP                   = 0,
441    SVGA_DC_CMD_START_STOP_CONTEXT    = 1,
442    SVGA_DC_CMD_PREEMPT               = 2,
443    SVGA_DC_CMD_MAX                   = 3,
444    SVGA_DC_CMD_FORCE_UINT            = MAX_UINT32,
445 } SVGADeviceContextCmdId;
446 
447 typedef struct {
448    uint32 enable;
449    SVGACBContext context;
450 } SVGADCCmdStartStop;
451 
452 /*
453  * SVGADCCmdPreempt --
454  *
455  * This command allows the guest to request that all command buffers
456  * on the specified context be preempted that can be.  After execution
457  * of this command all command buffers that were preempted will
458  * already have SVGA_CB_STATUS_PREEMPTED written into the status
459  * field.  The device might still be processing a command buffer,
460  * assuming execution of it started before the preemption request was
461  * received.  Specifying the ignoreIDZero flag to TRUE will cause the
462  * device to not preempt command buffers with the id field in the
463  * command buffer header set to zero.
464  */
465 
466 typedef struct {
467    SVGACBContext context;
468    uint32 ignoreIDZero;
469 } SVGADCCmdPreempt;
470 
471 
472 /*
473  * SVGAGMRImageFormat --
474  *
475  *    This is a packed representation of the source 2D image format
476  *    for a GMR-to-screen blit. Currently it is defined as an encoding
477  *    of the screen's color depth and bits-per-pixel, however, 16 bits
478  *    are reserved for future use to identify other encodings (such as
479  *    RGBA or higher-precision images).
480  *
481  *    Currently supported formats:
482  *
483  *       bpp depth  Format Name
484  *       --- -----  -----------
485  *        32    24  32-bit BGRX
486  *        24    24  24-bit BGR
487  *        16    16  RGB 5-6-5
488  *        16    15  RGB 5-5-5
489  *
490  */
491 
492 typedef struct SVGAGMRImageFormat {
493    union {
494       struct {
495          uint32 bitsPerPixel : 8;
496          uint32 colorDepth   : 8;
497 	 uint32 reserved     : 16;  /* Must be zero */
498       };
499 
500       uint32 value;
501    };
502 } SVGAGMRImageFormat;
503 
504 typedef
505 struct SVGAGuestImage {
506    SVGAGuestPtr         ptr;
507 
508    /*
509     * A note on interpretation of pitch: This value of pitch is the
510     * number of bytes between vertically adjacent image
511     * blocks. Normally this is the number of bytes between the first
512     * pixel of two adjacent scanlines. With compressed textures,
513     * however, this may represent the number of bytes between
514     * compression blocks rather than between rows of pixels.
515     *
516     * XXX: Compressed textures currently must be tightly packed in guest memory.
517     *
518     * If the image is 1-dimensional, pitch is ignored.
519     *
520     * If 'pitch' is zero, the SVGA3D device calculates a pitch value
521     * assuming each row of blocks is tightly packed.
522     */
523    uint32 pitch;
524 } SVGAGuestImage;
525 
526 /*
527  * SVGAColorBGRX --
528  *
529  *    A 24-bit color format (BGRX), which does not depend on the
530  *    format of the legacy guest framebuffer (GFB) or the current
531  *    GMRFB state.
532  */
533 
534 typedef struct SVGAColorBGRX {
535    union {
536       struct {
537          uint32 b : 8;
538          uint32 g : 8;
539          uint32 r : 8;
540 	     uint32 x : 8;  /* Unused */
541       };
542 
543       uint32 value;
544    };
545 } SVGAColorBGRX;
546 
547 
548 /*
549  * SVGASignedRect --
550  * SVGASignedPoint --
551  *
552  *    Signed rectangle and point primitives. These are used by the new
553  *    2D primitives for drawing to Screen Objects, which can occupy a
554  *    signed virtual coordinate space.
555  *
556  *    SVGASignedRect specifies a half-open interval: the (left, top)
557  *    pixel is part of the rectangle, but the (right, bottom) pixel is
558  *    not.
559  */
560 
561 typedef
562 struct {
563    int32  left;
564    int32  top;
565    int32  right;
566    int32  bottom;
567 } SVGASignedRect;
568 
569 typedef
570 struct {
571    int32  x;
572    int32  y;
573 } SVGASignedPoint;
574 
575 
576 /*
577  * SVGA Device Capabilities
578  *
579  * Note the holes in the bitfield. Missing bits have been deprecated,
580  * and must not be reused. Those capabilities will never be reported
581  * by new versions of the SVGA device.
582  *
583  * XXX: Add longer descriptions for each capability, including a list
584  *      of the new features that each capability provides.
585  *
586  * SVGA_CAP_IRQMASK --
587  *    Provides device interrupts.  Adds device register SVGA_REG_IRQMASK
588  *    to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
589  *    set/clear pending interrupts.
590  *
591  * SVGA_CAP_GMR --
592  *    Provides synchronous mapping of guest memory regions (GMR).
593  *    Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
594  *    SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
595  *
596  * SVGA_CAP_TRACES --
597  *    Allows framebuffer trace-based updates even when FIFO is enabled.
598  *    Adds device register SVGA_REG_TRACES.
599  *
600  * SVGA_CAP_GMR2 --
601  *    Provides asynchronous commands to define and remap guest memory
602  *    regions.  Adds device registers SVGA_REG_GMRS_MAX_PAGES and
603  *    SVGA_REG_MEMORY_SIZE.
604  *
605  * SVGA_CAP_SCREEN_OBJECT_2 --
606  *    Allow screen object support, and require backing stores from the
607  *    guest for each screen object.
608  *
609  * SVGA_CAP_COMMAND_BUFFERS --
610  *    Enable register based command buffer submission.
611  *
612  * SVGA_CAP_DEAD1 --
613  *    This cap was incorrectly used by old drivers and should not be
614  *    reused.
615  *
616  * SVGA_CAP_CMD_BUFFERS_2 --
617  *    Enable support for the prepend command buffer submision
618  *    registers.  SVGA_REG_CMD_PREPEND_LOW and
619  *    SVGA_REG_CMD_PREPEND_HIGH.
620  *
621  * SVGA_CAP_GBOBJECTS --
622  *    Enable guest-backed objects and surfaces.
623  *
624  * SVGA_CAP_CMD_BUFFERS_3 --
625  *    Enable support for command buffers in a mob.
626  */
627 
628 #define SVGA_CAP_NONE               0x00000000
629 #define SVGA_CAP_RECT_COPY          0x00000002
630 #define SVGA_CAP_CURSOR             0x00000020
631 #define SVGA_CAP_CURSOR_BYPASS      0x00000040
632 #define SVGA_CAP_CURSOR_BYPASS_2    0x00000080
633 #define SVGA_CAP_8BIT_EMULATION     0x00000100
634 #define SVGA_CAP_ALPHA_CURSOR       0x00000200
635 #define SVGA_CAP_3D                 0x00004000
636 #define SVGA_CAP_EXTENDED_FIFO      0x00008000
637 #define SVGA_CAP_MULTIMON           0x00010000
638 #define SVGA_CAP_PITCHLOCK          0x00020000
639 #define SVGA_CAP_IRQMASK            0x00040000
640 #define SVGA_CAP_DISPLAY_TOPOLOGY   0x00080000
641 #define SVGA_CAP_GMR                0x00100000
642 #define SVGA_CAP_TRACES             0x00200000
643 #define SVGA_CAP_GMR2               0x00400000
644 #define SVGA_CAP_SCREEN_OBJECT_2    0x00800000
645 #define SVGA_CAP_COMMAND_BUFFERS    0x01000000
646 #define SVGA_CAP_DEAD1              0x02000000
647 #define SVGA_CAP_CMD_BUFFERS_2      0x04000000
648 #define SVGA_CAP_GBOBJECTS          0x08000000
649 #define SVGA_CAP_CMD_BUFFERS_3      0x10000000
650 
651 #define SVGA_CAP_CAP2_REGISTER      0x80000000
652 
653 
654 /*
655  * The SVGA_REG_CAP2 register is an additional set of SVGA capability bits.
656  *
657  * SVGA_CAP2_GROW_OTABLE --
658  *      Allow the GrowOTable/DXGrowCOTable commands.
659  *
660  * SVGA_CAP2_INTRA_SURFACE_COPY --
661  *      Allow the IntraSurfaceCopy command.
662  *
663  * SVGA_CAP2_RESERVED --
664  *      Reserve the last bit for extending the SVGA capabilities to some
665  *      future mechanisms.
666  */
667 #define SVGA_CAP2_NONE               0x00000000
668 #define SVGA_CAP2_GROW_OTABLE        0x00000001
669 #define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
670 #define SVGA_CAP2_RESERVED           0x80000000
671 
672 /*
673  * The Guest can optionally read some SVGA device capabilities through
674  * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
675  * the SVGA device is initialized.  The type of capability the guest
676  * is requesting from the SVGABackdoorCapType enum should be placed in
677  * the upper 16 bits of the backdoor command id (ECX).  On success the
678  * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
679  * the requested capability.  If the command is not supported then EBX
680  * will be left unchanged and EAX will be set to -1.  Because it is
681  * possible that -1 is the value of the requested cap the correct way
682  * to check if the command was successful is to check if EBX was changed
683  * to BDOOR_MAGIC making sure to initialize the register to something
684  * else first.
685  */
686 
687 typedef enum {
688    SVGABackdoorCapDeviceCaps = 0,
689    SVGABackdoorCapFifoCaps = 1,
690    SVGABackdoorCap3dHWVersion = 2,
691    SVGABackdoorCapMax = 3,
692 } SVGABackdoorCapType;
693 
694 
695 /*
696  * FIFO register indices.
697  *
698  * The FIFO is a chunk of device memory mapped into guest physmem.  It
699  * is always treated as 32-bit words.
700  *
701  * The guest driver gets to decide how to partition it between
702  * - FIFO registers (there are always at least 4, specifying where the
703  *   following data area is and how much data it contains; there may be
704  *   more registers following these, depending on the FIFO protocol
705  *   version in use)
706  * - FIFO data, written by the guest and slurped out by the VMX.
707  * These indices are 32-bit word offsets into the FIFO.
708  */
709 
710 enum {
711    /*
712     * Block 1 (basic registers): The originally defined FIFO registers.
713     * These exist and are valid for all versions of the FIFO protocol.
714     */
715 
716    SVGA_FIFO_MIN = 0,
717    SVGA_FIFO_MAX,       /* The distance from MIN to MAX must be at least 10K */
718    SVGA_FIFO_NEXT_CMD,
719    SVGA_FIFO_STOP,
720 
721    /*
722     * Block 2 (extended registers): Mandatory registers for the extended
723     * FIFO.  These exist if the SVGA caps register includes
724     * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
725     * associated capability bit is enabled.
726     *
727     * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
728     * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
729     * This means that the guest has to test individually (in most cases
730     * using FIFO caps) for the presence of registers after this; the VMX
731     * can define "extended FIFO" to mean whatever it wants, and currently
732     * won't enable it unless there's room for that set and much more.
733     */
734 
735    SVGA_FIFO_CAPABILITIES = 4,
736    SVGA_FIFO_FLAGS,
737    /* Valid with SVGA_FIFO_CAP_FENCE: */
738    SVGA_FIFO_FENCE,
739 
740    /*
741     * Block 3a (optional extended registers): Additional registers for the
742     * extended FIFO, whose presence isn't actually implied by
743     * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
744     * leave room for them.
745     *
746     * These in block 3a, the VMX currently considers mandatory for the
747     * extended FIFO.
748     */
749 
750    /* Valid if exists (i.e. if extended FIFO enabled): */
751    SVGA_FIFO_3D_HWVERSION,       /* See SVGA3dHardwareVersion in svga3d_reg.h */
752    /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */
753    SVGA_FIFO_PITCHLOCK,
754 
755    /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */
756    SVGA_FIFO_CURSOR_ON,          /* Cursor bypass 3 show/hide register */
757    SVGA_FIFO_CURSOR_X,           /* Cursor bypass 3 x register */
758    SVGA_FIFO_CURSOR_Y,           /* Cursor bypass 3 y register */
759    SVGA_FIFO_CURSOR_COUNT,       /* Incremented when any of the other 3 change */
760    SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
761 
762    /* Valid with SVGA_FIFO_CAP_RESERVE: */
763    SVGA_FIFO_RESERVED,           /* Bytes past NEXT_CMD with real contents */
764 
765    /*
766     * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
767     *
768     * By default this is SVGA_ID_INVALID, to indicate that the cursor
769     * coordinates are specified relative to the virtual root. If this
770     * is set to a specific screen ID, cursor position is reinterpreted
771     * as a signed offset relative to that screen's origin.
772     */
773    SVGA_FIFO_CURSOR_SCREEN_ID,
774 
775    /*
776     * Valid with SVGA_FIFO_CAP_DEAD
777     *
778     * An arbitrary value written by the host, drivers should not use it.
779     */
780    SVGA_FIFO_DEAD,
781 
782    /*
783     * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
784     *
785     * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
786     * on platforms that can enforce graphics resource limits.
787     */
788    SVGA_FIFO_3D_HWVERSION_REVISED,
789 
790    /*
791     * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
792     * registers, but this must be done carefully and with judicious use of
793     * capability bits, since comparisons based on SVGA_FIFO_MIN aren't
794     * enough to tell you whether the register exists: we've shipped drivers
795     * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
796     * the earlier ones.  The actual order of introduction was:
797     * - PITCHLOCK
798     * - 3D_CAPS
799     * - CURSOR_* (cursor bypass 3)
800     * - RESERVED
801     * So, code that wants to know whether it can use any of the
802     * aforementioned registers, or anything else added after PITCHLOCK and
803     * before 3D_CAPS, needs to reason about something other than
804     * SVGA_FIFO_MIN.
805     */
806 
807    /*
808     * 3D caps block space; valid with 3D hardware version >=
809     * SVGA3D_HWVERSION_WS6_B1.
810     */
811    SVGA_FIFO_3D_CAPS      = 32,
812    SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
813 
814    /*
815     * End of VMX's current definition of "extended-FIFO registers".
816     * Registers before here are always enabled/disabled as a block; either
817     * the extended FIFO is enabled and includes all preceding registers, or
818     * it's disabled entirely.
819     *
820     * Block 3b (truly optional extended registers): Additional registers for
821     * the extended FIFO, which the VMX already knows how to enable and
822     * disable with correct granularity.
823     *
824     * Registers after here exist if and only if the guest SVGA driver
825     * sets SVGA_FIFO_MIN high enough to leave room for them.
826     */
827 
828    /* Valid if register exists: */
829    SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
830    SVGA_FIFO_FENCE_GOAL,         /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
831    SVGA_FIFO_BUSY,               /* See "FIFO Synchronization Registers" */
832 
833    /*
834     * Always keep this last.  This defines the maximum number of
835     * registers we know about.  At power-on, this value is placed in
836     * the SVGA_REG_MEM_REGS register, and we expect the guest driver
837     * to allocate this much space in FIFO memory for registers.
838     */
839     SVGA_FIFO_NUM_REGS
840 };
841 
842 
843 /*
844  * Definition of registers included in extended FIFO support.
845  *
846  * The guest SVGA driver gets to allocate the FIFO between registers
847  * and data.  It must always allocate at least 4 registers, but old
848  * drivers stopped there.
849  *
850  * The VMX will enable extended FIFO support if and only if the guest
851  * left enough room for all registers defined as part of the mandatory
852  * set for the extended FIFO.
853  *
854  * Note that the guest drivers typically allocate the FIFO only at
855  * initialization time, not at mode switches, so it's likely that the
856  * number of FIFO registers won't change without a reboot.
857  *
858  * All registers less than this value are guaranteed to be present if
859  * svgaUser->fifo.extended is set. Any later registers must be tested
860  * individually for compatibility at each use (in the VMX).
861  *
862  * This value is used only by the VMX, so it can change without
863  * affecting driver compatibility; keep it that way?
864  */
865 #define SVGA_FIFO_EXTENDED_MANDATORY_REGS  (SVGA_FIFO_3D_CAPS_LAST + 1)
866 
867 
868 /*
869  * FIFO Synchronization Registers
870  *
871  *  This explains the relationship between the various FIFO
872  *  sync-related registers in IOSpace and in FIFO space.
873  *
874  *  SVGA_REG_SYNC --
875  *
876  *       The SYNC register can be used in two different ways by the guest:
877  *
878  *         1. If the guest wishes to fully sync (drain) the FIFO,
879  *            it will write once to SYNC then poll on the BUSY
880  *            register. The FIFO is sync'ed once BUSY is zero.
881  *
882  *         2. If the guest wants to asynchronously wake up the host,
883  *            it will write once to SYNC without polling on BUSY.
884  *            Ideally it will do this after some new commands have
885  *            been placed in the FIFO, and after reading a zero
886  *            from SVGA_FIFO_BUSY.
887  *
888  *       (1) is the original behaviour that SYNC was designed to
889  *       support.  Originally, a write to SYNC would implicitly
890  *       trigger a read from BUSY. This causes us to synchronously
891  *       process the FIFO.
892  *
893  *       This behaviour has since been changed so that writing SYNC
894  *       will *not* implicitly cause a read from BUSY. Instead, it
895  *       makes a channel call which asynchronously wakes up the MKS
896  *       thread.
897  *
898  *       New guests can use this new behaviour to implement (2)
899  *       efficiently. This lets guests get the host's attention
900  *       without waiting for the MKS to poll, which gives us much
901  *       better CPU utilization on SMP hosts and on UP hosts while
902  *       we're blocked on the host GPU.
903  *
904  *       Old guests shouldn't notice the behaviour change. SYNC was
905  *       never guaranteed to process the entire FIFO, since it was
906  *       bounded to a particular number of CPU cycles. Old guests will
907  *       still loop on the BUSY register until the FIFO is empty.
908  *
909  *       Writing to SYNC currently has the following side-effects:
910  *
911  *         - Sets SVGA_REG_BUSY to TRUE (in the monitor)
912  *         - Asynchronously wakes up the MKS thread for FIFO processing
913  *         - The value written to SYNC is recorded as a "reason", for
914  *           stats purposes.
915  *
916  *       If SVGA_FIFO_BUSY is available, drivers are advised to only
917  *       write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
918  *       SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
919  *       eventually set SVGA_FIFO_BUSY on its own, but this approach
920  *       lets the driver avoid sending multiple asynchronous wakeup
921  *       messages to the MKS thread.
922  *
923  *  SVGA_REG_BUSY --
924  *
925  *       This register is set to TRUE when SVGA_REG_SYNC is written,
926  *       and it reads as FALSE when the FIFO has been completely
927  *       drained.
928  *
929  *       Every read from this register causes us to synchronously
930  *       process FIFO commands. There is no guarantee as to how many
931  *       commands each read will process.
932  *
933  *       CPU time spent processing FIFO commands will be billed to
934  *       the guest.
935  *
936  *       New drivers should avoid using this register unless they
937  *       need to guarantee that the FIFO is completely drained. It
938  *       is overkill for performing a sync-to-fence. Older drivers
939  *       will use this register for any type of synchronization.
940  *
941  *  SVGA_FIFO_BUSY --
942  *
943  *       This register is a fast way for the guest driver to check
944  *       whether the FIFO is already being processed. It reads and
945  *       writes at normal RAM speeds, with no monitor intervention.
946  *
947  *       If this register reads as TRUE, the host is guaranteeing that
948  *       any new commands written into the FIFO will be noticed before
949  *       the MKS goes back to sleep.
950  *
951  *       If this register reads as FALSE, no such guarantee can be
952  *       made.
953  *
954  *       The guest should use this register to quickly determine
955  *       whether or not it needs to wake up the host. If the guest
956  *       just wrote a command or group of commands that it would like
957  *       the host to begin processing, it should:
958  *
959  *         1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
960  *            action is necessary.
961  *
962  *         2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
963  *            code that we've already sent a SYNC to the host and we
964  *            don't need to send a duplicate.
965  *
966  *         3. Write a reason to SVGA_REG_SYNC. This will send an
967  *            asynchronous wakeup to the MKS thread.
968  */
969 
970 
971 /*
972  * FIFO Capabilities
973  *
974  *      Fence -- Fence register and command are supported
975  *      Accel Front -- Front buffer only commands are supported
976  *      Pitch Lock -- Pitch lock register is supported
977  *      Video -- SVGA Video overlay units are supported
978  *      Escape -- Escape command is supported
979  *
980  * XXX: Add longer descriptions for each capability, including a list
981  *      of the new features that each capability provides.
982  *
983  * SVGA_FIFO_CAP_SCREEN_OBJECT --
984  *
985  *    Provides dynamic multi-screen rendering, for improved Unity and
986  *    multi-monitor modes. With Screen Object, the guest can
987  *    dynamically create and destroy 'screens', which can represent
988  *    Unity windows or virtual monitors. Screen Object also provides
989  *    strong guarantees that DMA operations happen only when
990  *    guest-initiated. Screen Object deprecates the BAR1 guest
991  *    framebuffer (GFB) and all commands that work only with the GFB.
992  *
993  *    New registers:
994  *       FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
995  *
996  *    New 2D commands:
997  *       DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
998  *       BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
999  *
1000  *    New 3D commands:
1001  *       BLIT_SURFACE_TO_SCREEN
1002  *
1003  *    New guarantees:
1004  *
1005  *       - The host will not read or write guest memory, including the GFB,
1006  *         except when explicitly initiated by a DMA command.
1007  *
1008  *       - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
1009  *         is guaranteed to complete before any subsequent FENCEs.
1010  *
1011  *       - All legacy commands which affect a Screen (UPDATE, PRESENT,
1012  *         PRESENT_READBACK) as well as new Screen blit commands will
1013  *         all behave consistently as blits, and memory will be read
1014  *         or written in FIFO order.
1015  *
1016  *         For example, if you PRESENT from one SVGA3D surface to multiple
1017  *         places on the screen, the data copied will always be from the
1018  *         SVGA3D surface at the time the PRESENT was issued in the FIFO.
1019  *         This was not necessarily true on devices without Screen Object.
1020  *
1021  *         This means that on devices that support Screen Object, the
1022  *         PRESENT_READBACK command should not be necessary unless you
1023  *         actually want to read back the results of 3D rendering into
1024  *         system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
1025  *         command provides a strict superset of functionality.)
1026  *
1027  *       - When a screen is resized, either using Screen Object commands or
1028  *         legacy multimon registers, its contents are preserved.
1029  *
1030  * SVGA_FIFO_CAP_GMR2 --
1031  *
1032  *    Provides new commands to define and remap guest memory regions (GMR).
1033  *
1034  *    New 2D commands:
1035  *       DEFINE_GMR2, REMAP_GMR2.
1036  *
1037  * SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
1038  *
1039  *    Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
1040  *    This register may replace SVGA_FIFO_3D_HWVERSION on platforms
1041  *    that enforce graphics resource limits.  This allows the platform
1042  *    to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
1043  *    drivers that do not limit their resources.
1044  *
1045  *    Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
1046  *    are codependent (and thus we use a single capability bit).
1047  *
1048  * SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
1049  *
1050  *    Modifies the DEFINE_SCREEN command to include a guest provided
1051  *    backing store in GMR memory and the bytesPerLine for the backing
1052  *    store.  This capability requires the use of a backing store when
1053  *    creating screen objects.  However if SVGA_FIFO_CAP_SCREEN_OBJECT
1054  *    is present then backing stores are optional.
1055  *
1056  * SVGA_FIFO_CAP_DEAD --
1057  *
1058  *    Drivers should not use this cap bit.  This cap bit can not be
1059  *    reused since some hosts already expose it.
1060  */
1061 
1062 #define SVGA_FIFO_CAP_NONE                  0
1063 #define SVGA_FIFO_CAP_FENCE             (1<<0)
1064 #define SVGA_FIFO_CAP_ACCELFRONT        (1<<1)
1065 #define SVGA_FIFO_CAP_PITCHLOCK         (1<<2)
1066 #define SVGA_FIFO_CAP_VIDEO             (1<<3)
1067 #define SVGA_FIFO_CAP_CURSOR_BYPASS_3   (1<<4)
1068 #define SVGA_FIFO_CAP_ESCAPE            (1<<5)
1069 #define SVGA_FIFO_CAP_RESERVE           (1<<6)
1070 #define SVGA_FIFO_CAP_SCREEN_OBJECT     (1<<7)
1071 #define SVGA_FIFO_CAP_GMR2              (1<<8)
1072 #define SVGA_FIFO_CAP_3D_HWVERSION_REVISED  SVGA_FIFO_CAP_GMR2
1073 #define SVGA_FIFO_CAP_SCREEN_OBJECT_2   (1<<9)
1074 #define SVGA_FIFO_CAP_DEAD              (1<<10)
1075 
1076 
1077 /*
1078  * FIFO Flags
1079  *
1080  *      Accel Front -- Driver should use front buffer only commands
1081  */
1082 
1083 #define SVGA_FIFO_FLAG_NONE                 0
1084 #define SVGA_FIFO_FLAG_ACCELFRONT       (1<<0)
1085 #define SVGA_FIFO_FLAG_RESERVED        (1<<31) /* Internal use only */
1086 
1087 /*
1088  * FIFO reservation sentinel value
1089  */
1090 
1091 #define SVGA_FIFO_RESERVED_UNKNOWN      0xffffffff
1092 
1093 
1094 /*
1095  * Video overlay support
1096  */
1097 
1098 #define SVGA_NUM_OVERLAY_UNITS 32
1099 
1100 
1101 /*
1102  * Video capabilities that the guest is currently using
1103  */
1104 
1105 #define SVGA_VIDEO_FLAG_COLORKEY        0x0001
1106 
1107 
1108 /*
1109  * Offsets for the video overlay registers
1110  */
1111 
1112 enum {
1113    SVGA_VIDEO_ENABLED = 0,
1114    SVGA_VIDEO_FLAGS,
1115    SVGA_VIDEO_DATA_OFFSET,
1116    SVGA_VIDEO_FORMAT,
1117    SVGA_VIDEO_COLORKEY,
1118    SVGA_VIDEO_SIZE,          /* Deprecated */
1119    SVGA_VIDEO_WIDTH,
1120    SVGA_VIDEO_HEIGHT,
1121    SVGA_VIDEO_SRC_X,
1122    SVGA_VIDEO_SRC_Y,
1123    SVGA_VIDEO_SRC_WIDTH,
1124    SVGA_VIDEO_SRC_HEIGHT,
1125    SVGA_VIDEO_DST_X,         /* Signed int32 */
1126    SVGA_VIDEO_DST_Y,         /* Signed int32 */
1127    SVGA_VIDEO_DST_WIDTH,
1128    SVGA_VIDEO_DST_HEIGHT,
1129    SVGA_VIDEO_PITCH_1,
1130    SVGA_VIDEO_PITCH_2,
1131    SVGA_VIDEO_PITCH_3,
1132    SVGA_VIDEO_DATA_GMRID,    /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */
1133    SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */
1134                              /* (SVGA_ID_INVALID) */
1135    SVGA_VIDEO_NUM_REGS
1136 };
1137 
1138 
1139 /*
1140  * SVGA Overlay Units
1141  *
1142  *      width and height relate to the entire source video frame.
1143  *      srcX, srcY, srcWidth and srcHeight represent subset of the source
1144  *      video frame to be displayed.
1145  */
1146 
1147 typedef struct SVGAOverlayUnit {
1148    uint32 enabled;
1149    uint32 flags;
1150    uint32 dataOffset;
1151    uint32 format;
1152    uint32 colorKey;
1153    uint32 size;
1154    uint32 width;
1155    uint32 height;
1156    uint32 srcX;
1157    uint32 srcY;
1158    uint32 srcWidth;
1159    uint32 srcHeight;
1160    int32  dstX;
1161    int32  dstY;
1162    uint32 dstWidth;
1163    uint32 dstHeight;
1164    uint32 pitches[3];
1165    uint32 dataGMRId;
1166    uint32 dstScreenId;
1167 } SVGAOverlayUnit;
1168 
1169 
1170 /*
1171  * Guest display topology
1172  *
1173  * XXX: This structure is not part of the SVGA device's interface, and
1174  * doesn't really belong here.
1175  */
1176 #define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
1177 
1178 typedef struct SVGADisplayTopology {
1179    uint16 displayId;
1180    uint16 isPrimary;
1181    uint32 width;
1182    uint32 height;
1183    uint32 positionX;
1184    uint32 positionY;
1185 } SVGADisplayTopology;
1186 
1187 
1188 /*
1189  * SVGAScreenObject --
1190  *
1191  *    This is a new way to represent a guest's multi-monitor screen or
1192  *    Unity window. Screen objects are only supported if the
1193  *    SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
1194  *
1195  *    If Screen Objects are supported, they can be used to fully
1196  *    replace the functionality provided by the framebuffer registers
1197  *    (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
1198  *
1199  *    The screen object is a struct with guaranteed binary
1200  *    compatibility. New flags can be added, and the struct may grow,
1201  *    but existing fields must retain their meaning.
1202  *
1203  *    Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
1204  *    a SVGAGuestPtr that is used to back the screen contents.  This
1205  *    memory must come from the GFB.  The guest is not allowed to
1206  *    access the memory and doing so will have undefined results.  The
1207  *    backing store is required to be page aligned and the size is
1208  *    padded to the next page boundry.  The number of pages is:
1209  *       (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
1210  *
1211  *    The pitch in the backingStore is required to be at least large
1212  *    enough to hold a 32bbp scanline.  It is recommended that the
1213  *    driver pad bytesPerLine for a potential performance win.
1214  *
1215  *    The cloneCount field is treated as a hint from the guest that
1216  *    the user wants this display to be cloned, countCount times.  A
1217  *    value of zero means no cloning should happen.
1218  */
1219 
1220 #define SVGA_SCREEN_MUST_BE_SET     (1 << 0)
1221 #define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */
1222 #define SVGA_SCREEN_IS_PRIMARY      (1 << 1)
1223 #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)
1224 
1225 /*
1226  * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2.  When the screen is
1227  * deactivated the base layer is defined to lose all contents and
1228  * become black.  When a screen is deactivated the backing store is
1229  * optional.  When set backingPtr and bytesPerLine will be ignored.
1230  */
1231 #define SVGA_SCREEN_DEACTIVATE  (1 << 3)
1232 
1233 /*
1234  * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2.  When this flag is set
1235  * the screen contents will be outputted as all black to the user
1236  * though the base layer contents is preserved.  The screen base layer
1237  * can still be read and written to like normal though the no visible
1238  * effect will be seen by the user.  When the flag is changed the
1239  * screen will be blanked or redrawn to the current contents as needed
1240  * without any extra commands from the driver.  This flag only has an
1241  * effect when the screen is not deactivated.
1242  */
1243 #define SVGA_SCREEN_BLANKING (1 << 4)
1244 
1245 typedef
1246 struct {
1247    uint32 structSize;   /* sizeof(SVGAScreenObject) */
1248    uint32 id;
1249    uint32 flags;
1250    struct {
1251       uint32 width;
1252       uint32 height;
1253    } size;
1254    struct {
1255       int32 x;
1256       int32 y;
1257    } root;
1258 
1259    /*
1260     * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
1261     * with SVGA_FIFO_CAP_SCREEN_OBJECT.
1262     */
1263    SVGAGuestImage backingStore;
1264 
1265    /*
1266     * The cloneCount field is treated as a hint from the guest that
1267     * the user wants this display to be cloned, cloneCount times.
1268     *
1269     * A value of zero means no cloning should happen.
1270     */
1271    uint32 cloneCount;
1272 } SVGAScreenObject;
1273 
1274 
1275 /*
1276  *  Commands in the command FIFO:
1277  *
1278  *  Command IDs defined below are used for the traditional 2D FIFO
1279  *  communication (not all commands are available for all versions of the
1280  *  SVGA FIFO protocol).
1281  *
1282  *  Note the holes in the command ID numbers: These commands have been
1283  *  deprecated, and the old IDs must not be reused.
1284  *
1285  *  Command IDs from 1000 to 2999 are reserved for use by the SVGA3D
1286  *  protocol.
1287  *
1288  *  Each command's parameters are described by the comments and
1289  *  structs below.
1290  */
1291 
1292 typedef enum {
1293    SVGA_CMD_INVALID_CMD           = 0,
1294    SVGA_CMD_UPDATE                = 1,
1295    SVGA_CMD_RECT_COPY             = 3,
1296    SVGA_CMD_RECT_ROP_COPY         = 14,
1297    SVGA_CMD_DEFINE_CURSOR         = 19,
1298    SVGA_CMD_DEFINE_ALPHA_CURSOR   = 22,
1299    SVGA_CMD_UPDATE_VERBOSE        = 25,
1300    SVGA_CMD_FRONT_ROP_FILL        = 29,
1301    SVGA_CMD_FENCE                 = 30,
1302    SVGA_CMD_ESCAPE                = 33,
1303    SVGA_CMD_DEFINE_SCREEN         = 34,
1304    SVGA_CMD_DESTROY_SCREEN        = 35,
1305    SVGA_CMD_DEFINE_GMRFB          = 36,
1306    SVGA_CMD_BLIT_GMRFB_TO_SCREEN  = 37,
1307    SVGA_CMD_BLIT_SCREEN_TO_GMRFB  = 38,
1308    SVGA_CMD_ANNOTATION_FILL       = 39,
1309    SVGA_CMD_ANNOTATION_COPY       = 40,
1310    SVGA_CMD_DEFINE_GMR2           = 41,
1311    SVGA_CMD_REMAP_GMR2            = 42,
1312    SVGA_CMD_DEAD                  = 43,
1313    SVGA_CMD_DEAD_2                = 44,
1314    SVGA_CMD_NOP                   = 45,
1315    SVGA_CMD_NOP_ERROR             = 46,
1316    SVGA_CMD_MAX
1317 } SVGAFifoCmdId;
1318 
1319 #define SVGA_CMD_MAX_DATASIZE       (256 * 1024)
1320 #define SVGA_CMD_MAX_ARGS           64
1321 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) // 32 KB
1322 
1323 
1324 /*
1325  * SVGA_CMD_UPDATE --
1326  *
1327  *    This is a DMA transfer which copies from the Guest Framebuffer
1328  *    (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
1329  *    intersect with the provided virtual rectangle.
1330  *
1331  *    This command does not support using arbitrary guest memory as a
1332  *    data source- it only works with the pre-defined GFB memory.
1333  *    This command also does not support signed virtual coordinates.
1334  *    If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
1335  *    negative root x/y coordinates, the negative portion of those
1336  *    screens will not be reachable by this command.
1337  *
1338  *    This command is not necessary when using framebuffer
1339  *    traces. Traces are automatically enabled if the SVGA FIFO is
1340  *    disabled, and you may explicitly enable/disable traces using
1341  *    SVGA_REG_TRACES. With traces enabled, any write to the GFB will
1342  *    automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
1343  *
1344  *    Traces and SVGA_CMD_UPDATE are the only supported ways to render
1345  *    pseudocolor screen updates. The newer Screen Object commands
1346  *    only support true color formats.
1347  *
1348  * Availability:
1349  *    Always available.
1350  */
1351 
1352 typedef
1353 struct {
1354    uint32 x;
1355    uint32 y;
1356    uint32 width;
1357    uint32 height;
1358 } SVGAFifoCmdUpdate;
1359 
1360 
1361 /*
1362  * SVGA_CMD_RECT_COPY --
1363  *
1364  *    Perform a rectangular DMA transfer from one area of the GFB to
1365  *    another, and copy the result to any screens which intersect it.
1366  *
1367  * Availability:
1368  *    SVGA_CAP_RECT_COPY
1369  */
1370 
1371 typedef
1372 struct {
1373    uint32 srcX;
1374    uint32 srcY;
1375    uint32 destX;
1376    uint32 destY;
1377    uint32 width;
1378    uint32 height;
1379 } SVGAFifoCmdRectCopy;
1380 
1381 
1382 /*
1383  * SVGA_CMD_RECT_ROP_COPY --
1384  *
1385  *    Perform a rectangular DMA transfer from one area of the GFB to
1386  *    another, and copy the result to any screens which intersect it.
1387  *    The value of ROP may only be SVGA_ROP_COPY, and this command is
1388  *    only supported for backwards compatibility reasons.
1389  *
1390  * Availability:
1391  *    SVGA_CAP_RECT_COPY
1392  */
1393 
1394 typedef
1395 struct {
1396    uint32 srcX;
1397    uint32 srcY;
1398    uint32 destX;
1399    uint32 destY;
1400    uint32 width;
1401    uint32 height;
1402    uint32 rop;
1403 } SVGAFifoCmdRectRopCopy;
1404 
1405 
1406 /*
1407  * SVGA_CMD_DEFINE_CURSOR --
1408  *
1409  *    Provide a new cursor image, as an AND/XOR mask.
1410  *
1411  *    The recommended way to position the cursor overlay is by using
1412  *    the SVGA_FIFO_CURSOR_* registers, supported by the
1413  *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1414  *
1415  * Availability:
1416  *    SVGA_CAP_CURSOR
1417  */
1418 
1419 typedef
1420 struct {
1421    uint32 id;             /* Reserved, must be zero. */
1422    uint32 hotspotX;
1423    uint32 hotspotY;
1424    uint32 width;
1425    uint32 height;
1426    uint32 andMaskDepth;   /* Value must be 1 or equal to BITS_PER_PIXEL */
1427    uint32 xorMaskDepth;   /* Value must be 1 or equal to BITS_PER_PIXEL */
1428    /*
1429     * Followed by scanline data for AND mask, then XOR mask.
1430     * Each scanline is padded to a 32-bit boundary.
1431    */
1432 } SVGAFifoCmdDefineCursor;
1433 
1434 
1435 /*
1436  * SVGA_CMD_DEFINE_ALPHA_CURSOR --
1437  *
1438  *    Provide a new cursor image, in 32-bit BGRA format.
1439  *
1440  *    The recommended way to position the cursor overlay is by using
1441  *    the SVGA_FIFO_CURSOR_* registers, supported by the
1442  *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1443  *
1444  * Availability:
1445  *    SVGA_CAP_ALPHA_CURSOR
1446  */
1447 
1448 typedef
1449 struct {
1450    uint32 id;             /* Reserved, must be zero. */
1451    uint32 hotspotX;
1452    uint32 hotspotY;
1453    uint32 width;
1454    uint32 height;
1455    /* Followed by scanline data */
1456 } SVGAFifoCmdDefineAlphaCursor;
1457 
1458 
1459 /*
1460  * SVGA_CMD_UPDATE_VERBOSE --
1461  *
1462  *    Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
1463  *    'reason' value, an opaque cookie which is used by internal
1464  *    debugging tools. Third party drivers should not use this
1465  *    command.
1466  *
1467  * Availability:
1468  *    SVGA_CAP_EXTENDED_FIFO
1469  */
1470 
1471 typedef
1472 struct {
1473    uint32 x;
1474    uint32 y;
1475    uint32 width;
1476    uint32 height;
1477    uint32 reason;
1478 } SVGAFifoCmdUpdateVerbose;
1479 
1480 
1481 /*
1482  * SVGA_CMD_FRONT_ROP_FILL --
1483  *
1484  *    This is a hint which tells the SVGA device that the driver has
1485  *    just filled a rectangular region of the GFB with a solid
1486  *    color. Instead of reading these pixels from the GFB, the device
1487  *    can assume that they all equal 'color'. This is primarily used
1488  *    for remote desktop protocols.
1489  *
1490  * Availability:
1491  *    SVGA_FIFO_CAP_ACCELFRONT
1492  */
1493 
1494 #define  SVGA_ROP_COPY                    0x03
1495 
1496 typedef
1497 struct {
1498    uint32 color;     /* In the same format as the GFB */
1499    uint32 x;
1500    uint32 y;
1501    uint32 width;
1502    uint32 height;
1503    uint32 rop;       /* Must be SVGA_ROP_COPY */
1504 } SVGAFifoCmdFrontRopFill;
1505 
1506 
1507 /*
1508  * SVGA_CMD_FENCE --
1509  *
1510  *    Insert a synchronization fence.  When the SVGA device reaches
1511  *    this command, it will copy the 'fence' value into the
1512  *    SVGA_FIFO_FENCE register. It will also compare the fence against
1513  *    SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
1514  *    SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
1515  *    raise this interrupt.
1516  *
1517  * Availability:
1518  *    SVGA_FIFO_FENCE for this command,
1519  *    SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
1520  */
1521 
1522 typedef
1523 struct {
1524    uint32 fence;
1525 } SVGAFifoCmdFence;
1526 
1527 
1528 /*
1529  * SVGA_CMD_ESCAPE --
1530  *
1531  *    Send an extended or vendor-specific variable length command.
1532  *    This is used for video overlay, third party plugins, and
1533  *    internal debugging tools. See svga_escape.h
1534  *
1535  * Availability:
1536  *    SVGA_FIFO_CAP_ESCAPE
1537  */
1538 
1539 typedef
1540 struct {
1541    uint32 nsid;
1542    uint32 size;
1543    /* followed by 'size' bytes of data */
1544 } SVGAFifoCmdEscape;
1545 
1546 
1547 /*
1548  * SVGA_CMD_DEFINE_SCREEN --
1549  *
1550  *    Define or redefine an SVGAScreenObject. See the description of
1551  *    SVGAScreenObject above.  The video driver is responsible for
1552  *    generating new screen IDs. They should be small positive
1553  *    integers. The virtual device will have an implementation
1554  *    specific upper limit on the number of screen IDs
1555  *    supported. Drivers are responsible for recycling IDs. The first
1556  *    valid ID is zero.
1557  *
1558  *    - Interaction with other registers:
1559  *
1560  *    For backwards compatibility, when the GFB mode registers (WIDTH,
1561  *    HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1562  *    deletes all screens other than screen #0, and redefines screen
1563  *    #0 according to the specified mode. Drivers that use
1564  *    SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
1565  *
1566  *    If you use screen objects, do not use the legacy multi-mon
1567  *    registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
1568  *
1569  * Availability:
1570  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1571  */
1572 
1573 typedef
1574 struct {
1575    SVGAScreenObject screen;   /* Variable-length according to version */
1576 } SVGAFifoCmdDefineScreen;
1577 
1578 
1579 /*
1580  * SVGA_CMD_DESTROY_SCREEN --
1581  *
1582  *    Destroy an SVGAScreenObject. Its ID is immediately available for
1583  *    re-use.
1584  *
1585  * Availability:
1586  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1587  */
1588 
1589 typedef
1590 struct {
1591    uint32 screenId;
1592 } SVGAFifoCmdDestroyScreen;
1593 
1594 
1595 /*
1596  * SVGA_CMD_DEFINE_GMRFB --
1597  *
1598  *    This command sets a piece of SVGA device state called the
1599  *    Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
1600  *    piece of light-weight state which identifies the location and
1601  *    format of an image in guest memory or in BAR1. The GMRFB has
1602  *    an arbitrary size, and it doesn't need to match the geometry
1603  *    of the GFB or any screen object.
1604  *
1605  *    The GMRFB can be redefined as often as you like. You could
1606  *    always use the same GMRFB, you could redefine it before
1607  *    rendering from a different guest screen, or you could even
1608  *    redefine it before every blit.
1609  *
1610  *    There are multiple ways to use this command. The simplest way is
1611  *    to use it to move the framebuffer either to elsewhere in the GFB
1612  *    (BAR1) memory region, or to a user-defined GMR. This lets a
1613  *    driver use a framebuffer allocated entirely out of normal system
1614  *    memory, which we encourage.
1615  *
1616  *    Another way to use this command is to set up a ring buffer of
1617  *    updates in GFB memory. If a driver wants to ensure that no
1618  *    frames are skipped by the SVGA device, it is important that the
1619  *    driver not modify the source data for a blit until the device is
1620  *    done processing the command. One efficient way to accomplish
1621  *    this is to use a ring of small DMA buffers. Each buffer is used
1622  *    for one blit, then we move on to the next buffer in the
1623  *    ring. The FENCE mechanism is used to protect each buffer from
1624  *    re-use until the device is finished with that buffer's
1625  *    corresponding blit.
1626  *
1627  *    This command does not affect the meaning of SVGA_CMD_UPDATE.
1628  *    UPDATEs always occur from the legacy GFB memory area. This
1629  *    command has no support for pseudocolor GMRFBs. Currently only
1630  *    true-color 15, 16, and 24-bit depths are supported. Future
1631  *    devices may expose capabilities for additional framebuffer
1632  *    formats.
1633  *
1634  *    The default GMRFB value is undefined. Drivers must always send
1635  *    this command at least once before performing any blit from the
1636  *    GMRFB.
1637  *
1638  * Availability:
1639  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1640  */
1641 
1642 typedef
1643 struct {
1644    SVGAGuestPtr        ptr;
1645    uint32              bytesPerLine;
1646    SVGAGMRImageFormat  format;
1647 } SVGAFifoCmdDefineGMRFB;
1648 
1649 
1650 /*
1651  * SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
1652  *
1653  *    This is a guest-to-host blit. It performs a DMA operation to
1654  *    copy a rectangular region of pixels from the current GMRFB to
1655  *    one or more Screen Objects.
1656  *
1657  *    The destination coordinate may be specified relative to a
1658  *    screen's origin (if a screen ID is specified) or relative to the
1659  *    virtual coordinate system's origin (if the screen ID is
1660  *    SVGA_ID_INVALID). The actual destination may span zero or more
1661  *    screens, in the case of a virtual destination rect or a rect
1662  *    which extends off the edge of the specified screen.
1663  *
1664  *    This command writes to the screen's "base layer": the underlying
1665  *    framebuffer which exists below any cursor or video overlays. No
1666  *    action is necessary to explicitly hide or update any overlays
1667  *    which exist on top of the updated region.
1668  *
1669  *    The SVGA device is guaranteed to finish reading from the GMRFB
1670  *    by the time any subsequent FENCE commands are reached.
1671  *
1672  *    This command consumes an annotation. See the
1673  *    SVGA_CMD_ANNOTATION_* commands for details.
1674  *
1675  * Availability:
1676  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1677  */
1678 
1679 typedef
1680 struct {
1681    SVGASignedPoint  srcOrigin;
1682    SVGASignedRect   destRect;
1683    uint32           destScreenId;
1684 } SVGAFifoCmdBlitGMRFBToScreen;
1685 
1686 
1687 /*
1688  * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
1689  *
1690  *    This is a host-to-guest blit. It performs a DMA operation to
1691  *    copy a rectangular region of pixels from a single Screen Object
1692  *    back to the current GMRFB.
1693  *
1694  *    Usage note: This command should be used rarely. It will
1695  *    typically be inefficient, but it is necessary for some types of
1696  *    synchronization between 3D (GPU) and 2D (CPU) rendering into
1697  *    overlapping areas of a screen.
1698  *
1699  *    The source coordinate is specified relative to a screen's
1700  *    origin. The provided screen ID must be valid. If any parameters
1701  *    are invalid, the resulting pixel values are undefined.
1702  *
1703  *    This command reads the screen's "base layer". Overlays like
1704  *    video and cursor are not included, but any data which was sent
1705  *    using a blit-to-screen primitive will be available, no matter
1706  *    whether the data's original source was the GMRFB or the 3D
1707  *    acceleration hardware.
1708  *
1709  *    Note that our guest-to-host blits and host-to-guest blits aren't
1710  *    symmetric in their current implementation. While the parameters
1711  *    are identical, host-to-guest blits are a lot less featureful.
1712  *    They do not support clipping: If the source parameters don't
1713  *    fully fit within a screen, the blit fails. They must originate
1714  *    from exactly one screen. Virtual coordinates are not directly
1715  *    supported.
1716  *
1717  *    Host-to-guest blits do support the same set of GMRFB formats
1718  *    offered by guest-to-host blits.
1719  *
1720  *    The SVGA device is guaranteed to finish writing to the GMRFB by
1721  *    the time any subsequent FENCE commands are reached.
1722  *
1723  * Availability:
1724  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1725  */
1726 
1727 typedef
1728 struct {
1729    SVGASignedPoint  destOrigin;
1730    SVGASignedRect   srcRect;
1731    uint32           srcScreenId;
1732 } SVGAFifoCmdBlitScreenToGMRFB;
1733 
1734 
1735 /*
1736  * SVGA_CMD_ANNOTATION_FILL --
1737  *
1738  *    This is a blit annotation. This command stores a small piece of
1739  *    device state which is consumed by the next blit-to-screen
1740  *    command. The state is only cleared by commands which are
1741  *    specifically documented as consuming an annotation. Other
1742  *    commands (such as ESCAPEs for debugging) may intervene between
1743  *    the annotation and its associated blit.
1744  *
1745  *    This annotation is a promise about the contents of the next
1746  *    blit: The video driver is guaranteeing that all pixels in that
1747  *    blit will have the same value, specified here as a color in
1748  *    SVGAColorBGRX format.
1749  *
1750  *    The SVGA device can still render the blit correctly even if it
1751  *    ignores this annotation, but the annotation may allow it to
1752  *    perform the blit more efficiently, for example by ignoring the
1753  *    source data and performing a fill in hardware.
1754  *
1755  *    This annotation is most important for performance when the
1756  *    user's display is being remoted over a network connection.
1757  *
1758  * Availability:
1759  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1760  */
1761 
1762 typedef
1763 struct {
1764    SVGAColorBGRX  color;
1765 } SVGAFifoCmdAnnotationFill;
1766 
1767 
1768 /*
1769  * SVGA_CMD_ANNOTATION_COPY --
1770  *
1771  *    This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more
1772  *    information about annotations.
1773  *
1774  *    This annotation is a promise about the contents of the next
1775  *    blit: The video driver is guaranteeing that all pixels in that
1776  *    blit will have the same value as those which already exist at an
1777  *    identically-sized region on the same or a different screen.
1778  *
1779  *    Note that the source pixels for the COPY in this annotation are
1780  *    sampled before applying the anqnotation's associated blit. They
1781  *    are allowed to overlap with the blit's destination pixels.
1782  *
1783  *    The copy source rectangle is specified the same way as the blit
1784  *    destination: it can be a rectangle which spans zero or more
1785  *    screens, specified relative to either a screen or to the virtual
1786  *    coordinate system's origin. If the source rectangle includes
1787  *    pixels which are not from exactly one screen, the results are
1788  *    undefined.
1789  *
1790  * Availability:
1791  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1792  */
1793 
1794 typedef
1795 struct {
1796    SVGASignedPoint  srcOrigin;
1797    uint32           srcScreenId;
1798 } SVGAFifoCmdAnnotationCopy;
1799 
1800 
1801 /*
1802  * SVGA_CMD_DEFINE_GMR2 --
1803  *
1804  *    Define guest memory region v2.  See the description of GMRs above.
1805  *
1806  * Availability:
1807  *    SVGA_CAP_GMR2
1808  */
1809 
1810 typedef
1811 struct {
1812    uint32 gmrId;
1813    uint32 numPages;
1814 } SVGAFifoCmdDefineGMR2;
1815 
1816 
1817 /*
1818  * SVGA_CMD_REMAP_GMR2 --
1819  *
1820  *    Remap guest memory region v2.  See the description of GMRs above.
1821  *
1822  *    This command allows guest to modify a portion of an existing GMR by
1823  *    invalidating it or reassigning it to different guest physical pages.
1824  *    The pages are identified by physical page number (PPN).  The pages
1825  *    are assumed to be pinned and valid for DMA operations.
1826  *
1827  *    Description of command flags:
1828  *
1829  *    SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
1830  *       The PPN list must not overlap with the remap region (this can be
1831  *       handled trivially by referencing a separate GMR).  If flag is
1832  *       disabled, PPN list is appended to SVGARemapGMR command.
1833  *
1834  *    SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
1835  *       it is in PPN32 format.
1836  *
1837  *    SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
1838  *       A single PPN can be used to invalidate a portion of a GMR or
1839  *       map it to to a single guest scratch page.
1840  *
1841  * Availability:
1842  *    SVGA_CAP_GMR2
1843  */
1844 
1845 typedef enum {
1846    SVGA_REMAP_GMR2_PPN32         = 0,
1847    SVGA_REMAP_GMR2_VIA_GMR       = (1 << 0),
1848    SVGA_REMAP_GMR2_PPN64         = (1 << 1),
1849    SVGA_REMAP_GMR2_SINGLE_PPN    = (1 << 2),
1850 } SVGARemapGMR2Flags;
1851 
1852 typedef
1853 struct {
1854    uint32 gmrId;
1855    SVGARemapGMR2Flags flags;
1856    uint32 offsetPages; /* offset in pages to begin remap */
1857    uint32 numPages; /* number of pages to remap */
1858    /*
1859     * Followed by additional data depending on SVGARemapGMR2Flags.
1860     *
1861     * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
1862     * Otherwise an array of page descriptors in PPN32 or PPN64 format
1863     * (according to flag SVGA_REMAP_GMR2_PPN64) follows.  If flag
1864     * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
1865     */
1866 } SVGAFifoCmdRemapGMR2;
1867 
1868 
1869 /*
1870  * Size of SVGA device memory such as frame buffer and FIFO.
1871  */
1872 #define SVGA_VRAM_MIN_SIZE             (4 * 640 * 480) /* bytes */
1873 #define SVGA_VRAM_MIN_SIZE_3D       (16 * 1024 * 1024)
1874 #define SVGA_VRAM_MAX_SIZE         (128 * 1024 * 1024)
1875 #define SVGA_MEMORY_SIZE_MAX      (1024 * 1024 * 1024)
1876 #define SVGA_FIFO_SIZE_MAX           (2 * 1024 * 1024)
1877 #define SVGA_GRAPHICS_MEMORY_KB_MIN       (32 * 1024)
1878 #define SVGA_GRAPHICS_MEMORY_KB_MAX       (2 * 1024 * 1024)
1879 #define SVGA_GRAPHICS_MEMORY_KB_DEFAULT   (256 * 1024)
1880 
1881 #define SVGA_VRAM_SIZE_W2K          (64 * 1024 * 1024) /* 64 MB */
1882 
1883 /*
1884  * To simplify autoDetect display configuration, support a minimum of
1885  * two 1920x1200 monitors, 32bpp, side-by-side, optionally rotated:
1886  *   numDisplays = 2
1887  *   maxWidth = numDisplay * 1920 = 3840
1888  *   maxHeight = rotated width of single monitor = 1920
1889  *   vramSize = maxWidth * maxHeight * 4 = 29491200
1890  */
1891 #define SVGA_VRAM_SIZE_AUTODETECT   (32 * 1024 * 1024)
1892 
1893 #if defined(VMX86_SERVER)
1894 #define SVGA_VRAM_SIZE               (4 * 1024 * 1024)
1895 #define SVGA_VRAM_SIZE_3D           (64 * 1024 * 1024)
1896 #define SVGA_FIFO_SIZE                    (256 * 1024)
1897 #define SVGA_FIFO_SIZE_3D                 (516 * 1024)
1898 #define SVGA_MEMORY_SIZE_DEFAULT   (160 * 1024 * 1024)
1899 #define SVGA_AUTODETECT_DEFAULT                  FALSE
1900 #else
1901 #define SVGA_VRAM_SIZE              (16 * 1024 * 1024)
1902 #define SVGA_VRAM_SIZE_3D           SVGA_VRAM_MAX_SIZE
1903 #define SVGA_FIFO_SIZE               (2 * 1024 * 1024)
1904 #define SVGA_FIFO_SIZE_3D               SVGA_FIFO_SIZE
1905 #define SVGA_MEMORY_SIZE_DEFAULT   (768 * 1024 * 1024)
1906 #define SVGA_AUTODETECT_DEFAULT                   TRUE
1907 #endif
1908 
1909 #endif
1910