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Searched refs:constrainSelectedInstRegOperands (Results 1 – 22 of 22) sorted by relevance

/external/llvm-project/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
158 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
165 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
173 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
175 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
266 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedStore()
281 if (!constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI)) in buildUnalignedLoad()
305 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI)) in select()
329 if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI)) in select()
335 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) in select()
[all …]
DMipsLegalizerInfo.cpp515 return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI); in legalizeIntrinsic()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp146 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
152 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
159 return constrainSelectedInstRegOperands(*Inst, TII, TRI, RBI); in materialize32BitImm()
167 if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI)) in materialize32BitImm()
169 if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI)) in materialize32BitImm()
270 if (!constrainSelectedInstRegOperands(*Mul, TII, TRI, RBI)) in select()
294 if (!constrainSelectedInstRegOperands(*PseudoMULTu, TII, TRI, RBI)) in select()
300 if (!constrainSelectedInstRegOperands(*PseudoMove, TII, TRI, RBI)) in select()
343 if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI)) in select()
351 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select()
[all …]
DMipsLegalizerInfo.cpp377 return constrainSelectedInstRegOperands(*Trap, TII, TRI, RBI); in legalizeIntrinsic()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp1130 constrainSelectedInstRegOperands(*Shl, TII, TRI, RBI); in selectVectorSHL()
1172 constrainSelectedInstRegOperands(*Neg, TII, TRI, RBI); in selectVectorASHR()
1174 constrainSelectedInstRegOperands(*SShl, TII, TRI, RBI); in selectVectorASHR()
1198 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectVaStartDarwin()
1206 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectVaStartDarwin()
1223 constrainSelectedInstRegOperands(*MovZ, TII, TRI, RBI); in materializeLargeCMVal()
1240 constrainSelectedInstRegOperands(*MovI, TII, TRI, RBI); in materializeLargeCMVal()
1326 return constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI); in earlySelectSHL()
1426 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
1518 return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI); in select()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp584 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) in insertComparison()
592 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI)) in insertComparison()
603 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI)) in insertComparison()
702 if (!constrainSelectedInstRegOperands(*MIBLoad, TII, TRI, RBI)) in selectGlobal()
709 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal()
716 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal()
731 if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI)) in selectGlobal()
742 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal()
764 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal()
781 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) in selectSelect()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp586 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) in insertComparison()
594 if (!constrainSelectedInstRegOperands(*ReadI, TII, TRI, RBI)) in insertComparison()
605 if (!constrainSelectedInstRegOperands(*Mov1I, TII, TRI, RBI)) in insertComparison()
704 if (!constrainSelectedInstRegOperands(*MIBLoad, TII, TRI, RBI)) in selectGlobal()
711 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal()
718 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal()
733 if (!constrainSelectedInstRegOperands(*OffsetMIB, TII, TRI, RBI)) in selectGlobal()
744 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal()
766 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobal()
783 if (!constrainSelectedInstRegOperands(*CmpI, TII, TRI, RBI)) in selectSelect()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp1029 constrainSelectedInstRegOperands(*FCSel, TII, TRI, RBI); in emitSelect()
1176 constrainSelectedInstRegOperands(*SelectInst, TII, TRI, RBI); in emitSelect()
1414 constrainSelectedInstRegOperands(*TestBitMI, TII, TRI, RBI); in emitTestBit()
1473 constrainSelectedInstRegOperands(*BranchMI, TII, TRI, RBI); in emitCBZ()
1631 constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI); in selectCompareBranch()
1636 return constrainSelectedInstRegOperands(*Bcc, TII, TRI, RBI); in selectCompareBranch()
1740 constrainSelectedInstRegOperands(*Shl, TII, TRI, RBI); in selectVectorSHL()
1798 constrainSelectedInstRegOperands(*Neg, TII, TRI, RBI); in selectVectorAshrLshr()
1800 constrainSelectedInstRegOperands(*SShl, TII, TRI, RBI); in selectVectorAshrLshr()
1824 constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectVaStartDarwin()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp548 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectLoadStoreOp()
585 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectFrameIndexOrGep()
631 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectGlobalValue()
678 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectConstant()
831 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI); in selectZext()
936 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); in selectCmp()
937 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI); in selectCmp()
1003 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); in selectFCmp()
1004 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI); in selectFCmp()
1005 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI); in selectFCmp()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp547 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectLoadStoreOp()
584 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectFrameIndexOrGep()
630 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectGlobalValue()
677 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectConstant()
876 constrainSelectedInstRegOperands(AndInst, TII, TRI, RBI); in selectZext()
981 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); in selectCmp()
982 constrainSelectedInstRegOperands(SetInst, TII, TRI, RBI); in selectCmp()
1048 constrainSelectedInstRegOperands(CmpInst, TII, TRI, RBI); in selectFCmp()
1049 constrainSelectedInstRegOperands(Set1, TII, TRI, RBI); in selectFCmp()
1050 constrainSelectedInstRegOperands(Set2, TII, TRI, RBI); in selectFCmp()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp287 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_AND_OR_XOR()
311 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); in selectG_ADD_SUB()
319 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_ADD_SUB()
332 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); in selectG_ADD_SUB()
372 if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI)) in selectG_ADD_SUB()
411 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_UADDO_USUBO_UADDE_USUBE()
761 constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) && in selectG_ICMP()
777 bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI); in selectG_ICMP()
1022 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectStoreIntrinsic()
1104 bool Ret = constrainSelectedInstRegOperands(*DS, TII, TRI, RBI); in selectDSOrderedIntrinsic()
[all …]
DAMDGPURegisterBankInfo.cpp1429 if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this)) in selectStoreIntrinsic()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp296 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_AND_OR_XOR()
321 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); in selectG_ADD_SUB()
329 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_ADD_SUB()
342 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); in selectG_ADD_SUB()
382 if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI)) in selectG_ADD_SUB()
419 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_UADDO_USUBO_UADDE_USUBE()
668 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR_TRUNC()
672 return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); in selectG_BUILD_VECTOR_TRUNC()
852 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectWritelane()
893 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDivScale()
[all …]
DAMDGPURegisterBankInfo.cpp1581 if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this)) in applyMappingBFEIntrinsic()
1850 if (!constrainSelectedInstRegOperands(*MIB, *TII, *TRI, *this)) in selectStoreIntrinsic()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DUtils.h92 bool constrainSelectedInstRegOperands(MachineInstr &I,
DInstructionSelectorImpl.h995 constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI, in executeMatchTable()
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DUtils.h94 bool constrainSelectedInstRegOperands(MachineInstr &I,
DInstructionSelectorImpl.h1073 constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI, in executeMatchTable()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp111 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, in constrainSelectedInstRegOperands() function in llvm
/external/llvm-project/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h321 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in constrainAllUses()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h311 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); in constrainAllUses()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp125 bool llvm::constrainSelectedInstRegOperands(MachineInstr &I, in constrainSelectedInstRegOperands() function in llvm