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/external/llvm-project/llvm/test/CodeGen/X86/
Dpr46877.ll206 %81 = fsub reassoc nsz contract float %0, %1
207 %82 = fmul reassoc nsz contract float %1, %2
208 %83 = fmul reassoc nsz contract float %3, %82
209 %84 = fsub reassoc nsz contract float %0, %83
210 %85 = fmul reassoc nsz contract float %84, %4
211 %86 = fmul reassoc nsz contract float %81, %5
212 %87 = fsub reassoc nsz contract float %0, %86
213 %88 = fmul reassoc nsz contract float %87, %85
214 %89 = fmul reassoc nsz contract float %81, %6
215 %90 = fmul reassoc nsz contract float %89, %7
[all …]
Dsqrt-fastmath-mir.ll99 …; CHECK: [[VRSQRTSSr:%[0-9]+]]:fr32 = nnan ninf nsz arcp contract afn reassoc VRSQRTSSr killed […
100 …; CHECK: %3:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], [[VRSQR…
102 …; CHECK: %5:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr [[VRSQRTSSr]]…
104 …; CHECK: %7:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[VRSQRTSSr]], [[…
105 …; CHECK: %8:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %7, killed…
106 …; CHECK: %9:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr [[COPY]], %8, imp…
107 …; CHECK: %10:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VFMADD213SSr %8, killed %…
108 …; CHECK: %11:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr %8, [[VMOVSSrm_a…
109 …; CHECK: %12:fr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept VMULSSrr killed %11, kill…
123 …; CHECK: [[VRSQRTSSr:%[0-9]+]]:fr32 = nnan ninf nsz arcp contract afn reassoc VRSQRTSSr killed […
[all …]
Dpow.75.ll31 ; CHECK: Combining: {{.*}}: v4f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.…
32 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn re…
33 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract af…
34 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v4f32 = fmul nnan ninf nsz arcp contract afn reasso…
35 ; CHECK-NEXT: ... into: [[R]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQ…
41 ; CHECK: Combining: {{.*}}: v2f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.…
42 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn re…
43 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract af…
44 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v2f64 = fmul nnan ninf nsz arcp contract afn reasso…
45 ; CHECK-NEXT: ... into: [[R]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQ…
Dfmf-propagation.ll12 ; CHECK-NEXT: t9: f32 = fadd contract t8, t4
15 ; CHECK-NEXT: t12: f32 = fadd nnan ninf nsz arcp contract afn reassoc t11, t4
24 %f5 = fadd contract float %f4, %y
32 ; CHECK: t13: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, …
41 ; CHECK: t14: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, …
/external/llvm-project/mlir/test/Dialect/Vector/
Dvector-unroll-options.mlir5 %0 = vector.contract
14 // CHECK: vector.contract {
16 // CHECK: vector.contract {
18 // CHECK: vector.contract {
20 // CHECK: vector.contract {
22 // CHECK: vector.contract {
24 // CHECK: vector.contract {
26 // CHECK: vector.contract {
28 // CHECK: vector.contract {
30 // CHECK: vector.contract {
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dpow.75.ll32 ; CHECK: Combining: [[FIRST]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], Co…
33 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reas…
34 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn …
35 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc …
36 ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRT…
37 ; CHECK: Combining: [[SECOND]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], C…
38 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reas…
39 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn …
40 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc …
41 ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRT…
[all …]
/external/llvm-project/clang/test/CodeGen/
Dfp-contract-fast-pragma.cpp8 #pragma clang fp contract(fast) in fp_contract_1()
18 #pragma clang fp contract(fast) in fp_contract_2()
29 #pragma clang fp contract(fast) in template_muladd()
43 #pragma clang fp contract(fast) in method()
54 #pragma clang fp contract(fast)
63 #pragma clang fp contract(fast) contract(off)
Dfp-contract-on-pragma.cpp7 #pragma clang fp contract(on) in fp_contract_1()
17 #pragma clang fp contract(on) in fp_contract_2()
28 #pragma clang fp contract(on) in template_muladd()
41 #pragma clang fp contract(on) in method()
51 #pragma clang fp contract(on)
58 #pragma clang fp contract(off)
74 #pragma clang fp contract(on) in fp_contract_7()
/external/llvm-project/mlir/integration_test/Dialect/Vector/CPU/
Dtest-contraction.mlir202 %dp1 = vector.contract #dotp_trait %a, %b, %f0
204 %dp2 = vector.contract #dotp_trait %a, %b, %f1
216 %mv1 = vector.contract #matvec_trait %A, %c, %z1
218 %mv2 = vector.contract #matvec_trait %A, %c, %a
230 %mv3 = vector.contract #mattransvec_trait %A, %c, %z1
232 %mv4 = vector.contract #mattransvec_trait %A, %c, %a
244 %mm1 = vector.contract #matmat_trait %A, %B, %z2
246 %mm2 = vector.contract #matmat_trait %A, %B, %A
263 vector.contract #column_major_matmat_trait %A, %B, %z2
266 vector.contract #column_major_matmat_trait %A, %B, %A
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dneon-fma-FMF.ll7 %tmp1 = fmul contract <2 x float> %A, %B;
8 %tmp2 = fadd contract <2 x float> %C, %tmp1;
13 ; the contract on the fadd
18 %tmp2 = fadd contract <2 x float> %C, %tmp1;
26 %tmp1 = fmul contract <2 x float> %A, %B;
34 %tmp1 = fmul contract <2 x float> %A, %B;
35 %tmp2 = fsub contract <2 x float> %C, %tmp1;
40 ; the contract on the fsub
45 %tmp2 = fsub contract <2 x float> %C, %tmp1;
53 %tmp1 = fmul contract <2 x float> %A, %B;
Dmachine-combiner-instr-fmf.mir35 %3:fpr32 = nnan ninf nsz arcp contract afn reassoc FMULSrr %1, %0
36 %4:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr killed %3, %2
42 # Can create FMADD, because both the fmul and fadd have the contract fast-math flag.
75 %3:fpr32 = contract FMULSrr %1, %0
76 %4:fpr32 = contract FADDSrr killed %3, %2
82 # Do not create FMADD, because we don't have the contract flag on the FADD.
88 # CHECK-NEXT: [[MUL:%.*]]:fpr32 = contract FMULSrr [[B]], [[A]]
115 %3:fpr32 = contract FMULSrr %1, %0
122 # Do create FMADD, because we have the contract flag on the FADD.
156 %4:fpr32 = contract FADDSrr killed %3, %2
[all …]
Dpow.75.ll31 ; CHECK: Combining: {{.*}}: v4f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.…
32 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn re…
33 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract af…
34 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v4f32 = fmul nnan ninf nsz arcp contract afn reasso…
35 ; CHECK-NEXT: ... into: [[R]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQ…
41 ; CHECK: Combining: {{.*}}: v2f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.…
42 ; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn re…
43 ; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract af…
44 ; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v2f64 = fmul nnan ninf nsz arcp contract afn reasso…
45 ; CHECK-NEXT: ... into: [[R]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQ…
/external/llvm-project/clang/test/Parser/
Dpragma-fp.cpp20 #pragma clang fp contract on in test_3()
28 #pragma clang fp contract(while) in test_4()
36 #pragma clang fp contract(maybe) in test_5()
44 #pragma clang fp contract(fast in test_6()
52 #pragma clang fp contract(fast) * in test_7()
62 #pragma clang fp contract(fast) in test_8()
73 #pragma clang fp exceptions(maytrap) contract(fast) reassociate(on) in test_10()
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dfp-mul-14.ll9 %i = fmul contract float %arg, 0xBE6777A5C0000000
10 %i4 = fadd contract float %i, 1.000000e+00
11 %i5 = fmul contract float %arg, 0xBE6777A5C0000000
12 %i6 = fadd contract float %i5, 1.000000e+00
13 %i7 = fmul contract float %i4, 2.000000e+00
/external/eigen/unsupported/test/
Dcxx11_tensor_contraction.cpp33 typedef TensorEvaluator<decltype(mat1.contract(mat2, dims3)), DefaultDevice> Evaluator; in test_evals()
34 Evaluator eval(mat1.contract(mat2, dims3), DefaultDevice()); in test_evals()
53 typedef TensorEvaluator<decltype(mat1.contract(mat2, dims4)), DefaultDevice> Evaluator2; in test_evals()
54 Evaluator2 eval2(mat1.contract(mat2, dims4), DefaultDevice()); in test_evals()
68 typedef TensorEvaluator<decltype(mat1.contract(mat3, dims6)), DefaultDevice> Evaluator3; in test_evals()
69 Evaluator3 eval3(mat1.contract(mat3, dims6), DefaultDevice()); in test_evals()
91 Tensor<float, 0, DataLayout> scalar = vec1.contract(vec2, dims); in test_scalar()
112 typedef TensorEvaluator<decltype(mat1.contract(mat2, dims)), DefaultDevice> Evaluator; in test_multidims()
113 Evaluator eval(mat1.contract(mat2, dims), DefaultDevice()); in test_multidims()
146 typedef TensorEvaluator<decltype(mat4.contract(mat5, dims2)), DefaultDevice> Evaluator2; in test_multidims()
[all …]
Dcxx11_tensor_thread_pool.cpp89 t_result.device(thread_pool_device) = t_left.contract(t_right, dims); in test_multithread_contraction()
130 t_result.device(thread_pool_device) = t_left.contract(t_right, dims); in test_contraction_corner_cases()
145 t_result.device(thread_pool_device) = t_left.contract(t_right, dims); in test_contraction_corner_cases()
162 t_result.device(thread_pool_device) = t_left.contract(t_right, dims); in test_contraction_corner_cases()
180 t_result.device(thread_pool_device) = t_left.contract(t_right, dims); in test_contraction_corner_cases()
220 st_result = left.contract(right, dims); in test_multithread_contraction_agrees_with_singlethread()
223 tp_result.device(thread_pool_device) = left.contract(right, dims); in test_multithread_contraction_agrees_with_singlethread()
259 st_result = left.contract(right, dims); in test_full_contraction()
262 tp_result.device(thread_pool_device) = left.contract(right, dims); in test_full_contraction()
/external/llvm-project/llvm/test/CodeGen/MIR/X86/
Dfastmath.mir21 ; CHECK: %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
22 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
27 ; CHECK: %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
28 %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
29 ; CHECK: %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
30 %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
Dmircanon-flags.mir19 ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract VMULSSrr
22 ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = nsz arcp contract afn reassoc VMULSSrr
23 ; CHECK-NEXT: %bb0_{{[0-9]+}}__1:fr32 = contract afn reassoc VMULSSrr
30 %5:fr32 = contract VMULSSrr %4, %4, implicit $mxcsr
33 %8:fr32 = nsz arcp contract afn reassoc VMULSSrr %7, %7, implicit $mxcsr
34 %9:fr32 = contract afn reassoc VMULSSrr %8, %8, implicit $mxcsr
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dfma-aggr-FMF.ll12 %mul1 = fmul contract float %f1, %f2
13 %mul2 = fmul contract float %f3, %f4
14 %add = fadd contract float %mul1, %mul2
19 ; There is no contract on the mul with no extra use so we can't fuse that.
30 %mul1 = fmul contract float %f1, %f2
32 %add = fadd contract float %mul1, %mul2
Dfma-negate.ll20 %0 = fmul contract reassoc double %b, %c
21 %1 = fsub contract reassoc double %a, %0
39 %0 = fmul contract reassoc double %a, %b
40 %1 = fmul contract reassoc double %c, %d
41 %2 = fsub contract reassoc double %0, %1
59 %0 = fsub contract reassoc double -0.0, %a
60 %1 = call contract reassoc double @llvm.fma.f64(double %0, double %b,
78 %0 = fmul contract reassoc float %b, %c
79 %1 = fsub contract reassoc float %a, %0
97 %0 = fmul contract reassoc float %a, %b
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
Dfused_costs.ll1 …-denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileChe…
2 …dhsa -mcpu=gfx900 -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=on < %s | FileChe…
3 …dhsa -mcpu=gfx900 -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=fast < %s | FileC…
4 …-denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileChe…
5 …-denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileChe…
6 …dhsa -mcpu=gfx900 -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=on < %s | FileChe…
7 …dhsa -mcpu=gfx900 -denormal-fp-math-f32=ieee -denormal-fp-math=ieee -fp-contract=fast < %s | FileC…
8 …-denormal-fp-math-f32=preserve-sign -denormal-fp-math=preserve-sign -fp-contract=on < %s | FileChe…
24 ; ALL: estimated cost of 0 for instruction: %mul = fmul contract float
25 ; ALL: estimated cost of 1 for instruction: %add = fadd contract float
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dregbank-fma.mir21 …; CHECK: [[FMA:%[0-9]+]]:fpr(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY…
27 %3:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
47 …; CHECK: [[FMA:%[0-9]+]]:fpr(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA [[COPY]], [[COPY…
53 %3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FMA %0, %1, %2
/external/llvm-project/llvm/test/Transforms/LoopUnroll/AMDGPU/
Dunroll-analyze-small-loops.ll44 %mul3 = fmul contract float %M, %ld2
45 %add3 = fadd contract float %ld1, %mul3
50 %mul4 = fmul contract float %ld2, %M
51 %add4 = fadd contract float %ld3, %mul4
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfma.ll135 %tmp2 = fadd contract float %tmp, %tmp
136 %tmp3 = fmul contract float %tmp2, 4.0
137 %tmp4 = fsub contract float 1.0, %tmp3
138 %tmp5 = fadd contract float %tmp4, %tmp1
139 %tmp6 = fadd contract float %tmp1, %tmp1
140 %tmp7 = fmul contract float %tmp6, %tmp
141 %tmp8 = fsub contract float 1.0, %tmp7
142 %tmp9 = fmul contract float %tmp8, 8.0
143 %tmp10 = fadd contract float %tmp5, %tmp9
Dfmuladd.v2f16.ll1 …ds=false -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -fp-contract=on -verify-machin…
2 …ds=false -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -fp-contract=on -verify-machin…
3 …ds=false -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -fp-contract=fast -verify-mach…
4 …ds=false -march=amdgcn -mcpu=gfx900 -denormal-fp-math=preserve-sign -fp-contract=fast -verify-mach…
6 …lobal-loads=false -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -fp-contract=on -verify-machin…
7 …lobal-loads=false -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -fp-contract=on -verify-machin…
8 …lobal-loads=false -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -fp-contract=fast -verify-mach…
9 …lobal-loads=false -march=amdgcn -mcpu=gfx900 -denormal-fp-math=ieee -fp-contract=fast -verify-mach…
57 %r4 = fadd contract <2 x half> %r3, %r2

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