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Searched refs:cs_params (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen6_constant_state.c311 const struct brw_cs_parameters cs_params = brw_cs_get_parameters(brw); in brw_upload_cs_push_constants() local
313 brw_cs_push_const_total_size(cs_prog_data, cs_params.threads); in brw_upload_cs_push_constants()
340 for (unsigned t = 0; t < cs_params.threads; t++) { in brw_upload_cs_push_constants()
DgenX_state_upload.c4274 const struct brw_cs_parameters cs_params = brw_cs_get_parameters(brw); local
4366 ALIGN(cs_prog_data->push.per_thread.regs * cs_params.threads +
4372 brw_cs_push_const_total_size(cs_prog_data, cs_params.threads);
4385 cs_params.simd_size);
4394 .NumberofThreadsinGPGPUThreadGroup = cs_params.threads,
4497 const struct brw_cs_parameters cs_params = brw_cs_get_parameters(brw); local
4500 brw_cs_right_mask(cs_params.group_size, cs_params.simd_size);
4505 ggw.SIMDSize = cs_params.simd_size / 16;
4508 ggw.ThreadWidthCounterMaximum = cs_params.threads - 1;
/external/mesa3d/src/intel/vulkan/
Danv_pipeline.c1817 struct anv_cs_parameters cs_params = {}; in anv_cs_parameters() local
1819 cs_params.group_size = cs_prog_data->local_size[0] * in anv_cs_parameters()
1822 cs_params.simd_size = in anv_cs_parameters()
1824 cs_prog_data, cs_params.group_size); in anv_cs_parameters()
1825 cs_params.threads = DIV_ROUND_UP(cs_params.group_size, cs_params.simd_size); in anv_cs_parameters()
1827 return cs_params; in anv_cs_parameters()
DgenX_pipeline.c2366 const struct anv_cs_parameters cs_params = anv_cs_parameters(pipeline); local
2368 pipeline->cs_right_mask = brw_cs_right_mask(cs_params.group_size, cs_params.simd_size);
2371 ALIGN(cs_prog_data->push.per_thread.regs * cs_params.threads +
2425 brw_cs_prog_data_prog_offset(cs_prog_data, cs_params.simd_size),
2458 .NumberofThreadsinGPGPUThreadGroup = cs_params.threads,
Danv_cmd_buffer.c1043 const struct anv_cs_parameters cs_params = anv_cs_parameters(pipeline); in anv_cmd_buffer_cs_push_constants() local
1045 brw_cs_push_const_total_size(cs_prog_data, cs_params.threads); in anv_cmd_buffer_cs_push_constants()
1068 for (unsigned t = 0; t < cs_params.threads; t++) { in anv_cmd_buffer_cs_push_constants()
DgenX_cmd_buffer.c4546 const struct anv_cs_parameters cs_params = anv_cs_parameters(pipeline); in emit_gpgpu_walker() local
4551 ggw.SIMDSize = cs_params.simd_size / 16; in emit_gpgpu_walker()
4554 ggw.ThreadWidthCounterMaximum = cs_params.threads - 1; in emit_gpgpu_walker()