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Searched refs:csinv (Results 1 – 25 of 58) sorted by relevance

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/external/arm-optimized-routines/string/aarch64/
Dstrncmp-mte.S80 csinv endloop, diff, xzr, hi /* Last Dword or differences. */
171 csinv limit, limit, xzr, lo
251 csinv endloop, diff, xzr, hi /* If limit, set to all ones. */
279 csinv tmp3, syndrome, xzr, hi /* If limit, set to all ones. */
289 csinv tmp3, syndrome, xzr, hi /* If limit, set to all ones. */
Dstrncmp.S70 csinv endloop, diff, xzr, pl /* Last Dword or differences. */
Dstrcpy.S266 csinv data1, data1, xzr, lt
/external/llvm-project/llvm/test/MC/ARM/
Dthumbv8.1m.s1105 # CHECK: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
1106 # CHECK-FP: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
1107 # CHECK-NOLOB: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
1108 csinv lr, r5, zr, hs label
1113 csinv lr, r2, r2, mi label
1136 csinv r0, sp, r1, eq label
1138 csinv r0, pc, r1, eq label
1160 csinv r0, r0, r1, ge label
Dmve-scalar-shift.s82 # CHECK: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
83 # CHECK-NOMVE: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
84 csinv lr, r5, zr, hs label
88 csinv lr, r2, r2, mi label
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsat-add.ll30 ; CHECK-NEXT: csinv w0, w8, wzr, eq
44 ; CHECK-NEXT: csinv w0, w9, wzr, ls
73 ; CHECK-NEXT: csinv w0, w8, wzr, eq
87 ; CHECK-NEXT: csinv w0, w8, wzr, hs
113 ; CHECK-NEXT: csinv w0, w8, wzr, lo
125 ; CHECK-NEXT: csinv w0, w8, wzr, lo
151 ; CHECK-NEXT: csinv x0, x8, xzr, lo
163 ; CHECK-NEXT: csinv x0, x8, xzr, lo
177 ; CHECK-NEXT: csinv w8, w0, w1, lo
193 ; CHECK-NEXT: csinv w0, w8, wzr, eq
[all …]
Dcond-sel.ll107 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls
115 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
124 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
132 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
152 ; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt
160 ; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi
Dcond-sel-value-prop.ll67 ; CHECK: csinv x0, x[[REG]], xzr, ne
94 ; CHECK: csinv x0, x[[REG]], xzr, eq
105 ; CHECK: csinv w0, w[[REG]], wzr, eq
Duadd_sat.ll14 ; CHECK-NEXT: csinv w0, w8, wzr, lo
24 ; CHECK-NEXT: csinv x0, x8, xzr, lo
Duadd_sat_plus.ll15 ; CHECK-NEXT: csinv w0, w8, wzr, lo
26 ; CHECK-NEXT: csinv x0, x8, xzr, lo
Darm64-early-ifcvt.ll114 ; CHECK-NEXT: csinv w0, w1, w0, eq
132 ; CHECK-NEXT: csinv x0, x1, x0, eq
150 ; CHECK-NEXT: csinv w0, w1, w0, ne
168 ; CHECK-NEXT: csinv x0, x1, x0, ne
Duadd_sat_vec.ll382 ; CHECK-NEXT: csinv x3, x9, xzr, eq
383 ; CHECK-NEXT: csinv x2, x8, xzr, eq
392 ; CHECK-NEXT: csinv x8, x8, xzr, eq
393 ; CHECK-NEXT: csinv x1, x9, xzr, eq
Dwin64_vararg.ll128 ; CHECK: csinv w0, w0, wzr, ge
237 ; CHECK-DAG: csinv w0, w0, wzr, ge
/external/llvm/test/CodeGen/AArch64/
Dcond-sel.ll107 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls
115 ; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
124 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
132 ; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
152 ; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt
160 ; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi
Dfp16-v4-instructions.ll303 ; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, vc
304 ; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, vc
305 ; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, vc
306 ; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, vc
421 ; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, le
422 ; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, le
423 ; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, le
424 ; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, le
Darm64-early-ifcvt.ll114 ; CHECK-NEXT: csinv w0, w1, w0, eq
132 ; CHECK-NEXT: csinv x0, x1, x0, eq
150 ; CHECK-NEXT: csinv w0, w1, w0, ne
168 ; CHECK-NEXT: csinv x0, x1, x0, ne
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
DA55-basic-instructions.s398 csinv w1, w0, w19, ne label
399 csinv wzr, w5, w9, eq label
400 csinv w9, wzr, w30, gt label
401 csinv w1, w28, wzr, mi label
402 csinv x19, x23, x29, lt label
403 csinv xzr, x3, x4, ge label
404 csinv x5, xzr, x6, hs label
405 csinv x7, x8, xzr, lo label
419 csinv x3, xzr, xzr, nv label
434 csinv x1, x0, x0, al label
[all …]
/external/llvm-project/libc/AOR_v20.02/string/aarch64/
Dstrnlen.S152 csinv data1, data1, xzr, le
Dstrncmp.S73 csinv endloop, diff, xzr, pl /* Last Dword or differences. */
Dstrcpy.S265 csinv data1, data1, xzr, lt
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dthumbv8.1m.s29 # CHECK: csinv lr, r5, zr, hs @ encoding: [0x55,0xea,0x2f,0xae]
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dcsel.ll148 ; CHECK-NEXT: csinv r0, r1, r2, gt
161 ; CHECK-NEXT: csinv r0, r2, r1, le
/external/capstone/suite/MC/AArch64/
Dbasic-a64-instructions.s.cs516 0x01,0x10,0x93,0x5a = csinv w1, w0, w19, ne
517 0xbf,0x00,0x89,0x5a = csinv wzr, w5, w9, eq
518 0xe9,0xc3,0x9e,0x5a = csinv w9, wzr, w30, gt
519 0x81,0x43,0x9f,0x5a = csinv w1, w28, wzr, mi
520 0xf3,0xb2,0x9d,0xda = csinv x19, x23, x29, lt
521 0x7f,0xa0,0x84,0xda = csinv xzr, x3, x4, ge
522 0xe5,0x23,0x86,0xda = csinv x5, xzr, x6, hs
523 0x07,0x31,0x9f,0xda = csinv x7, x8, xzr, lo
/external/llvm-project/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s1365 csinv w1, w0, w19, ne
1366 csinv wzr, w5, w9, eq
1367 csinv w9, wzr, w30, gt
1368 csinv w1, w28, wzr, mi
1374 csinv x19, x23, x29, lt
1375 csinv xzr, x3, x4, ge
1376 csinv x5, xzr, x6, cs
1377 csinv x7, x8, xzr, cc
/external/llvm/test/MC/AArch64/
Dbasic-a64-instructions.s1365 csinv w1, w0, w19, ne
1366 csinv wzr, w5, w9, eq
1367 csinv w9, wzr, w30, gt
1368 csinv w1, w28, wzr, mi
1374 csinv x19, x23, x29, lt
1375 csinv xzr, x3, x4, ge
1376 csinv x5, xzr, x6, cs
1377 csinv x7, x8, xzr, cc

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