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Searched refs:csrrw (Results 1 – 9 of 9) sorted by relevance

/external/llvm-project/llvm/test/MC/RISCV/
Dcsr-aliases.s46 # CHECK-INST: csrrw t1, fcsr, t2
49 # CHECK-EXT-F-OFF: csrrw t1, fcsr, t2
50 csrrw t1, 3, t2 label
52 # CHECK-INST: csrrw zero, fcsr, t2
56 csrrw zero, 3, t2 label
58 # CHECK-INST: csrrw zero, fcsr, t2
62 csrrw zero, 3, t2 label
64 # CHECK-INST: csrrw t0, frm, zero
67 # CHECK-EXT-F-OFF: csrrw t0, frm
68 csrrw t0, 2, zero label
[all …]
Drvf-aliases-valid.s51 # CHECK-INST: csrrw t1, fcsr, t2
54 # CHECK-INST: csrrw zero, fcsr, t3
63 # CHECK-INST: csrrw t5, fcsr, t6
66 # CHECK-INST: csrrw zero, fcsr, s0
73 # CHECK-INST: csrrw t5, frm, t4
76 # CHECK-INST: csrrw zero, frm, t6
89 # CHECK-INST: csrrw a2, fflags, a1
92 # CHECK-INST: csrrw zero, fflags, a3
Drv32i-valid.s349 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
351 csrrw t0, 0xfff, t1 label
352 # CHECK-ASM-AND-OBJ: csrrw s0, 4095, s1
354 csrrw s0, ~(-4096), s1 label
355 # CHECK-ASM-AND-OBJ: csrrw s0, fflags, s1
357 csrrw s0, !0, s1 label
Drv32e-valid.s108 # CHECK-ASM-AND-OBJ: csrrw t0, 4095, t1
109 csrrw t0, 0xfff, t1 label
Drv32i-invalid.s24 csrrw a0, -1, a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4095] label
77 csrrw a0, %lo(1), a0 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 4… label
87 csrrw a0, foos, a0 # CHECK: :[[@LINE]]:11: error: operand must be a valid system register name or a… label
Drvi-aliases-valid.s213 # CHECK-S-OBJ-NOALIAS: csrrw zero, sscratch, s1
245 csrrw t0, 0x150, 0xf label
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td485 def CSRRW : CSR_ir<0b001, "csrrw">;
678 def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
/external/elfutils/tests/
Dtestfile-riscv64-dis1.expect.bz2 ... ,t1 141 220: f3 1f 43 00 csrrw t6,uie,t1 142 224: f3 2 ...
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td535 def CSRRW : CSR_ir<0b001, "csrrw">;
740 def : InstAlias<"csrrw $rd, $csr, $imm", (CSRRWI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;