1 #ifndef GEN4_RENDER_H 2 #define GEN4_RENDER_H 3 4 #include <stdint.h> 5 6 #define GEN4_3D(Pipeline, Opcode, Subopcode) ((3 << 29) | \ 7 ((Pipeline) << 27) | \ 8 ((Opcode) << 24) | \ 9 ((Subopcode) << 16)) 10 11 #define GEN4_URB_FENCE GEN4_3D(0, 0, 0) 12 # define UF0_CS_REALLOC (1 << 13) 13 # define UF0_VFE_REALLOC (1 << 12) 14 # define UF0_SF_REALLOC (1 << 11) 15 # define UF0_CLIP_REALLOC (1 << 10) 16 # define UF0_GS_REALLOC (1 << 9) 17 # define UF0_VS_REALLOC (1 << 8) 18 # define UF1_CLIP_FENCE_SHIFT 20 19 # define UF1_GS_FENCE_SHIFT 10 20 # define UF1_VS_FENCE_SHIFT 0 21 # define UF2_CS_FENCE_SHIFT 20 22 # define UF2_VFE_FENCE_SHIFT 10 23 # define UF2_SF_FENCE_SHIFT 0 24 25 #define GEN4_CS_URB_STATE GEN4_3D(0, 0, 1) 26 27 #define GEN4_STATE_BASE_ADDRESS GEN4_3D(0, 1, 1) 28 # define BASE_ADDRESS_MODIFY (1 << 0) 29 30 #define GEN4_STATE_SIP GEN4_3D(0, 1, 2) 31 32 #define GEN4_PIPELINE_SELECT GEN4_3D(0, 1, 4) 33 #define G4X_PIPELINE_SELECT GEN4_3D(1, 1, 4) 34 # define PIPELINE_SELECT_3D 0 35 # define PIPELINE_SELECT_MEDIA 1 36 37 #define GEN4_3DSTATE_PIPELINED_POINTERS GEN4_3D(3, 0, 0) 38 # define GEN4_GS_DISABLE 0 39 # define GEN4_GS_ENABLE 1 40 # define GEN4_CLIP_DISABLE 0 41 # define GEN4_CLIP_ENABLE 1 42 43 #define GEN4_3DSTATE_BINDING_TABLE_POINTERS GEN4_3D(3, 0, 1) 44 45 #define GEN4_3DSTATE_VERTEX_BUFFERS GEN4_3D(3, 0, 8) 46 # define GEN4_VB0_BUFFER_INDEX_SHIFT 27 47 # define GEN4_VB0_VERTEXDATA (0 << 26) 48 # define GEN4_VB0_INSTANCEDATA (1 << 26) 49 # define VB0_BUFFER_PITCH_SHIFT 0 50 51 #define GEN4_3DSTATE_VERTEX_ELEMENTS GEN4_3D(3, 0, 9) 52 # define GEN4_VE0_VERTEX_BUFFER_INDEX_SHIFT 27 53 # define GEN4_VE0_VALID (1 << 26) 54 # define VE0_FORMAT_SHIFT 16 55 # define VE0_OFFSET_SHIFT 0 56 # define VE1_VFCOMPONENT_0_SHIFT 28 57 # define VE1_VFCOMPONENT_1_SHIFT 24 58 # define VE1_VFCOMPONENT_2_SHIFT 20 59 # define VE1_VFCOMPONENT_3_SHIFT 16 60 # define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0 61 62 #define GEN4_VFCOMPONENT_NOSTORE 0 63 #define GEN4_VFCOMPONENT_STORE_SRC 1 64 #define GEN4_VFCOMPONENT_STORE_0 2 65 #define GEN4_VFCOMPONENT_STORE_1_FLT 3 66 #define GEN4_VFCOMPONENT_STORE_1_INT 4 67 #define GEN4_VFCOMPONENT_STORE_VID 5 68 #define GEN4_VFCOMPONENT_STORE_IID 6 69 #define GEN4_VFCOMPONENT_STORE_PID 7 70 71 #define GEN4_3DSTATE_DRAWING_RECTANGLE GEN4_3D(3, 1, 0) 72 73 #define GEN4_3DSTATE_DEPTH_BUFFER GEN4_3D(3, 1, 5) 74 # define GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29 75 # define GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18 76 77 #define GEN4_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 78 #define GEN4_DEPTHFORMAT_D32_FLOAT 1 79 #define GEN4_DEPTHFORMAT_D24_UNORM_S8_UINT 2 80 #define GEN4_DEPTHFORMAT_D24_UNORM_X8_UINT 3 81 #define GEN4_DEPTHFORMAT_D16_UNORM 5 82 83 #define GEN4_3DSTATE_CLEAR_PARAMS GEN4_3D(3, 1, 0x10) 84 # define GEN4_3DSTATE_DEPTH_CLEAR_VALID (1 << 15) 85 86 #define GEN4_3DPRIMITIVE GEN4_3D(3, 3, 0) 87 # define GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15) 88 # define GEN4_3DPRIMITIVE_VERTEX_RANDOM (1 << 15) 89 # define GEN4_3DPRIMITIVE_TOPOLOGY_SHIFT 10 90 91 #define _3DPRIM_POINTLIST 0x01 92 #define _3DPRIM_LINELIST 0x02 93 #define _3DPRIM_LINESTRIP 0x03 94 #define _3DPRIM_TRILIST 0x04 95 #define _3DPRIM_TRISTRIP 0x05 96 #define _3DPRIM_TRIFAN 0x06 97 #define _3DPRIM_QUADLIST 0x07 98 #define _3DPRIM_QUADSTRIP 0x08 99 #define _3DPRIM_LINELIST_ADJ 0x09 100 #define _3DPRIM_LINESTRIP_ADJ 0x0A 101 #define _3DPRIM_TRILIST_ADJ 0x0B 102 #define _3DPRIM_TRISTRIP_ADJ 0x0C 103 #define _3DPRIM_TRISTRIP_REVERSE 0x0D 104 #define _3DPRIM_POLYGON 0x0E 105 #define _3DPRIM_RECTLIST 0x0F 106 #define _3DPRIM_LINELOOP 0x10 107 #define _3DPRIM_POINTLIST_BF 0x11 108 #define _3DPRIM_LINESTRIP_CONT 0x12 109 #define _3DPRIM_LINESTRIP_BF 0x13 110 #define _3DPRIM_LINESTRIP_CONT_BF 0x14 111 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 112 113 #define GEN4_CULLMODE_BOTH 0 114 #define GEN4_CULLMODE_NONE 1 115 #define GEN4_CULLMODE_FRONT 2 116 #define GEN4_CULLMODE_BACK 3 117 118 #define GEN4_BORDER_COLOR_MODE_DEFAULT 0 119 #define GEN4_BORDER_COLOR_MODE_LEGACY 1 120 121 #define GEN4_MAPFILTER_NEAREST 0 122 #define GEN4_MAPFILTER_LINEAR 1 123 #define GEN4_MAPFILTER_ANISOTROPIC 2 124 #define GEN4_MAPFILTER_MONO 6 125 126 #define GEN4_MIPFILTER_NONE 0 127 #define GEN4_MIPFILTER_NEAREST 1 128 #define GEN4_MIPFILTER_LINEAR 3 129 130 #define GEN4_PREFILTER_ALWAYS 0 131 #define GEN4_PREFILTER_NEVER 1 132 #define GEN4_PREFILTER_LESS 2 133 #define GEN4_PREFILTER_EQUAL 3 134 #define GEN4_PREFILTER_LEQUAL 4 135 #define GEN4_PREFILTER_GREATER 5 136 #define GEN4_PREFILTER_NOTEQUAL 6 137 #define GEN4_PREFILTER_GEQUAL 7 138 139 #define GEN4_TEXCOORDMODE_WRAP 0 140 #define GEN4_TEXCOORDMODE_MIRROR 1 141 #define GEN4_TEXCOORDMODE_CLAMP 2 142 #define GEN4_TEXCOORDMODE_CUBE 3 143 #define GEN4_TEXCOORDMODE_CLAMP_BORDER 4 144 #define GEN4_TEXCOORDMODE_MIRROR_ONCE 5 145 146 #define GEN4_LOD_PRECLAMP_D3D 0 147 #define GEN4_LOD_PRECLAMP_OGL 1 148 149 /* The hardware supports two different modes for border color. The 150 * default (OpenGL) mode uses floating-point color channels, while the 151 * legacy mode uses 4 bytes. 152 * 153 * More significantly, the legacy mode respects the components of the 154 * border color for channels not present in the source, (whereas the 155 * default mode will ignore the border color's alpha channel and use 156 * alpha==1 for an RGB source, for example). 157 * 158 * The legacy mode matches the semantics specified by the Render 159 * extension. 160 */ 161 struct gen4_sampler_default_border_color { 162 float color[4]; 163 }; 164 165 struct gen4_sampler_legacy_border_color { 166 uint8_t color[4]; 167 }; 168 169 struct gen4_sampler_state { 170 struct { 171 uint32_t shadow_function:3; 172 uint32_t lod_bias:11; 173 uint32_t min_filter:3; 174 uint32_t mag_filter:3; 175 uint32_t mip_filter:2; 176 uint32_t base_level:5; 177 uint32_t pad0:1; 178 uint32_t lod_preclamp:1; 179 uint32_t border_color_mode:1; 180 uint32_t pad1:1; 181 uint32_t disable:1; 182 } ss0; 183 184 struct { 185 uint32_t r_wrap_mode:3; 186 uint32_t t_wrap_mode:3; 187 uint32_t s_wrap_mode:3; 188 uint32_t cube_ctlr_mode:1; 189 uint32_t pad:2; 190 uint32_t max_lod:10; 191 uint32_t min_lod:10; 192 } ss1; 193 194 struct { 195 uint32_t pad:5; 196 uint32_t border_color_pointer:27; 197 } ss2; 198 199 struct { 200 uint32_t pad:13; 201 uint32_t address_rounding_enable:6; 202 uint32_t max_aniso:3; 203 uint32_t chroma_key_mode:1; 204 uint32_t chroma_key_index:2; 205 uint32_t chroma_key_enable:1; 206 uint32_t monochrome_filter_width:3; 207 uint32_t monochrome_filter_height:3; 208 } ss3; 209 }; 210 211 typedef enum { 212 SAMPLER_FILTER_NEAREST = 0, 213 SAMPLER_FILTER_BILINEAR, 214 FILTER_COUNT 215 } sampler_filter_t; 216 217 typedef enum { 218 SAMPLER_EXTEND_NONE = 0, 219 SAMPLER_EXTEND_REPEAT, 220 SAMPLER_EXTEND_PAD, 221 SAMPLER_EXTEND_REFLECT, 222 EXTEND_COUNT 223 } sampler_extend_t; 224 225 struct gen4_surface_state { 226 struct { 227 unsigned int cube_pos_z:1; 228 unsigned int cube_neg_z:1; 229 unsigned int cube_pos_y:1; 230 unsigned int cube_neg_y:1; 231 unsigned int cube_pos_x:1; 232 unsigned int cube_neg_x:1; 233 unsigned int media_boundary_pixel_mode:2; 234 unsigned int render_cache_read_mode:1; 235 unsigned int cube_corner_mode:1; 236 unsigned int mipmap_layout_mode:1; 237 unsigned int vert_line_stride_ofs:1; 238 unsigned int vert_line_stride:1; 239 unsigned int color_blend:1; 240 unsigned int writedisable_blue:1; 241 unsigned int writedisable_green:1; 242 unsigned int writedisable_red:1; 243 unsigned int writedisable_alpha:1; 244 unsigned int surface_format:9; 245 unsigned int data_return_format:1; 246 unsigned int pad0:1; 247 unsigned int surface_type:3; 248 } ss0; 249 250 struct { 251 unsigned int base_addr; 252 } ss1; 253 254 struct { 255 unsigned int render_target_rotation:2; 256 unsigned int mip_count:4; 257 unsigned int width:13; 258 unsigned int height:13; 259 } ss2; 260 261 struct { 262 unsigned int tile_walk:1; 263 unsigned int tiled_surface:1; 264 unsigned int pad0:1; 265 unsigned int pitch:17; 266 unsigned int pad1:1; 267 unsigned int depth:11; 268 } ss3; 269 270 struct { 271 unsigned int pad:8; 272 unsigned int render_target_view_extent:9; 273 unsigned int min_array_elt:11; 274 unsigned int min_lod:4; 275 } ss4; 276 277 struct { 278 unsigned int pad:20; 279 unsigned int y_offset:4; 280 unsigned int pad1:1; 281 unsigned int x_offset:7; 282 } ss5; 283 }; 284 285 struct gen4_cc_viewport { 286 float min_depth; 287 float max_depth; 288 }; 289 290 struct gen4_vs_state { 291 struct { 292 unsigned int pad0:1; 293 unsigned int grf_reg_count:3; 294 unsigned int pad1:2; 295 unsigned int kernel_start_pointer:26; 296 } vs0; 297 298 struct { 299 unsigned int pad0:7; 300 unsigned int sw_exception_enable:1; 301 unsigned int pad1:3; 302 unsigned int mask_stack_exception_enable:1; 303 unsigned int pad2:1; 304 unsigned int illegal_op_exception_enable:1; 305 unsigned int pad3:2; 306 unsigned int floating_point_mode:1; 307 unsigned int thread_priority:1; 308 unsigned int binding_table_entry_count:8; 309 unsigned int pad4:5; 310 unsigned int single_program_flow:1; 311 } vs1; 312 313 struct { 314 unsigned int per_thread_scratch_space:4; 315 unsigned int pad0:6; 316 unsigned int scratch_space_pointer:22; 317 } vs2; 318 319 struct { 320 unsigned int dispatch_grf_start_reg:4; 321 unsigned int urb_entry_read_offset:6; 322 unsigned int pad0:1; 323 unsigned int urb_entry_read_length:6; 324 unsigned int pad1:1; 325 unsigned int const_urb_entry_read_offset:6; 326 unsigned int pad2:1; 327 unsigned int const_urb_entry_read_length:6; 328 unsigned int pad3:1; 329 } vs3; 330 331 struct { 332 unsigned int pad0:10; 333 unsigned int stats_enable:1; 334 unsigned int nr_urb_entries:7; 335 unsigned int pad1:1; 336 unsigned int urb_entry_allocation_size:5; 337 unsigned int pad2:1; 338 unsigned int max_threads:6; 339 unsigned int pad3:1; 340 } vs4; 341 342 struct { 343 unsigned int sampler_count:3; 344 unsigned int pad:2; 345 unsigned int sampler_state_pointer:27; 346 } vs5; 347 348 struct { 349 unsigned int vs_enable:1; 350 unsigned int vert_cache_disable:1; 351 unsigned int pad:30; 352 } vs6; 353 }; 354 355 struct gen4_sf_state { 356 struct { 357 unsigned int pad0:1; 358 unsigned int grf_reg_count:3; 359 unsigned int pad1:2; 360 unsigned int kernel_start_pointer:26; 361 } sf0; 362 363 struct { 364 unsigned int barycentric_interp:1; /* ilk */ 365 unsigned int pad0:6; 366 unsigned int sw_exception_enable:1; 367 unsigned int pad1:3; 368 unsigned int mask_stack_exception_enable:1; 369 unsigned int pad2:1; 370 unsigned int illegal_op_exception_enable:1; 371 unsigned int pad3:2; 372 unsigned int floating_point_mode:1; 373 unsigned int thread_priority:1; 374 unsigned int binding_table_entry_count:8; 375 unsigned int pad4:6; 376 } sf1; 377 378 struct { 379 unsigned int per_thread_scratch_space:4; 380 unsigned int pad0:6; 381 unsigned int scratch_space_pointer:22; 382 } sf2; 383 384 struct { 385 unsigned int dispatch_grf_start_reg:4; 386 unsigned int urb_entry_read_offset:6; 387 unsigned int pad0:1; 388 unsigned int urb_entry_read_length:7; 389 unsigned int const_urb_entry_read_offset:6; 390 unsigned int pad1:1; 391 unsigned int const_urb_entry_read_length:6; 392 unsigned int pad2:1; 393 } sf3; 394 395 struct { 396 unsigned int pad0:10; 397 unsigned int stats_enable:1; 398 unsigned int nr_urb_entries:8; 399 unsigned int urb_entry_allocation_size:6; 400 unsigned int max_threads:6; 401 unsigned int pad2:1; 402 } sf4; 403 404 struct { 405 unsigned int front_winding:1; 406 unsigned int viewport_transform:1; 407 unsigned int pad:3; 408 unsigned int sf_viewport_state_offset:27; 409 } sf5; 410 411 struct { 412 unsigned int pad:9; 413 unsigned int dest_org_vbias:4; 414 unsigned int dest_org_hbias:4; 415 unsigned int scissor:1; 416 unsigned int disable_2x2_trifilter:1; 417 unsigned int disable_zero_trifilter:1; 418 unsigned int point_rast_rule:2; 419 unsigned int line_endcap_aa_region_width:2; 420 unsigned int line_width:4; 421 unsigned int fast_scissor_disable:1; 422 unsigned int cull_mode:2; 423 unsigned int aa_enable:1; 424 } sf6; 425 426 struct { 427 unsigned int point_size:11; 428 unsigned int use_point_size_state:1; 429 unsigned int subpixel_precision:1; 430 unsigned int sprite_point:1; 431 unsigned int aa_line_dist_mode:1; 432 unsigned int pad:10; 433 unsigned int trifan_pv:2; 434 unsigned int linestrip_pv:2; 435 unsigned int tristrip_pv:2; 436 unsigned int line_last_pixel_enable:1; 437 } sf7; 438 }; 439 440 struct gen4_wm_state { 441 struct { 442 unsigned int pad0:1; 443 unsigned int grf_reg_count:3; 444 unsigned int pad1:2; 445 unsigned int kernel_start_pointer:26; 446 } wm0; 447 448 struct { 449 unsigned int pad0:1; 450 unsigned int sw_exception_enable:1; 451 unsigned int mask_stack_exception_enable:1; 452 unsigned int pad2:1; 453 unsigned int illegal_op_exception_enable:1; 454 unsigned int pad3:3; 455 unsigned int depth_coeff_urb_read_offset:6; 456 unsigned int pad4:2; 457 unsigned int floating_point_mode:1; 458 unsigned int thread_priority:1; 459 unsigned int binding_table_entry_count:8; 460 unsigned int pad5:5; 461 unsigned int single_program_flow:1; 462 } wm1; 463 464 struct { 465 unsigned int per_thread_scratch_space:4; 466 unsigned int pad0:6; 467 unsigned int scratch_space_pointer:22; 468 } wm2; 469 470 struct { 471 unsigned int dispatch_grf_start_reg:4; 472 unsigned int urb_entry_read_offset:6; 473 unsigned int pad0:1; 474 unsigned int urb_entry_read_length:7; 475 unsigned int const_urb_entry_read_offset:6; 476 unsigned int pad1:1; 477 unsigned int const_urb_entry_read_length:6; 478 unsigned int pad2:1; 479 } wm3; 480 481 struct { 482 unsigned int stats_enable:1; 483 unsigned int pad0:1; 484 unsigned int sampler_count:3; 485 unsigned int sampler_state_pointer:27; 486 } wm4; 487 488 struct { 489 unsigned int enable_8_pix:1; 490 unsigned int enable_16_pix:1; 491 unsigned int enable_32_pix:1; 492 unsigned int enable_cont_32_pix:1; /* ctg+ */ 493 unsigned int enable_cont_64_pix:1; /* ctg+ */ 494 unsigned int pad0:1; 495 unsigned int fast_span_coverage:1; /* ilk */ 496 unsigned int depth_clear:1; /* ilk */ 497 unsigned int depth_resolve:1; /* ilk */ 498 unsigned int hier_depth_resolve:1; /* ilk */ 499 unsigned int legacy_global_depth_bias:1; 500 unsigned int line_stipple:1; 501 unsigned int depth_offset:1; 502 unsigned int polygon_stipple:1; 503 unsigned int line_aa_region_width:2; 504 unsigned int line_endcap_aa_region_width:2; 505 unsigned int early_depth_test:1; 506 unsigned int thread_dispatch_enable:1; 507 unsigned int program_uses_depth:1; 508 unsigned int program_computes_dpeth:1; 509 unsigned int program_uses_killpixel:1; 510 unsigned int legacy_line_rast:1; 511 unsigned int transposed_urb_read:1; 512 unsigned int max_threads:7; 513 } wm5; 514 515 struct { 516 float global_depth_offset_constant; 517 } wm6; 518 519 struct { 520 float global_depth_offset_scale; 521 } wm7; 522 523 /* ilk only from now on */ 524 struct { 525 unsigned int pad0:1; 526 unsigned int grf_reg_count_1:3; 527 unsigned int pad1:2; 528 unsigned int kernel_start_pointer_1:26; 529 } wm8; 530 531 struct { 532 unsigned int pad0:1; 533 unsigned int grf_reg_count_2:3; 534 unsigned int pad1:2; 535 unsigned int kernel_start_pointer_2:26; 536 } wm9; 537 538 struct { 539 unsigned int pad0:1; 540 unsigned int grf_reg_count_3:3; 541 unsigned int pad1:2; 542 unsigned int kernel_start_pointer_3:26; 543 } wm10; 544 }; 545 546 struct gen4_color_calc_state { 547 struct { 548 unsigned int pad0:3; 549 unsigned int bf_stencil_pass_depth_pass_op:3; 550 unsigned int bf_stencil_pass_depth_fail_op:3; 551 unsigned int bf_stencil_fail_op:3; 552 unsigned int bf_stencil_func:3; 553 unsigned int bf_stencil_enable:1; 554 unsigned int pad1:2; 555 unsigned int stencil_write_enable:1; 556 unsigned int stencil_pass_depth_pass_op:3; 557 unsigned int stencil_pass_depth_fail_op:3; 558 unsigned int stencil_fail_op:3; 559 unsigned int stencil_func:3; 560 unsigned int stencil_enable:1; 561 } cc0; 562 563 struct { 564 unsigned int bf_stencil_ref:8; 565 unsigned int stencil_write_mask:8; 566 unsigned int stencil_test_mask:8; 567 unsigned int stencil_ref:8; 568 } cc1; 569 570 struct { 571 unsigned int logicop_enable:1; 572 unsigned int pad0:10; 573 unsigned int depth_write_enable:1; 574 unsigned int depth_test_function:3; 575 unsigned int depth_test:1; 576 unsigned int bf_stencil_write_mask:8; 577 unsigned int bf_stencil_test_mask:8; 578 } cc2; 579 580 struct { 581 unsigned int pad0:8; 582 unsigned int alpha_test_func:3; 583 unsigned int alpha_test:1; 584 unsigned int blend_enable:1; 585 unsigned int ia_blend_enable:1; 586 unsigned int pad1:1; 587 unsigned int alpha_test_format:1; 588 unsigned int pad2:16; 589 } cc3; 590 591 struct { 592 unsigned int pad0:5; 593 unsigned int cc_viewport_state_offset:27; 594 } cc4; 595 596 struct { 597 unsigned int pad0:2; 598 unsigned int ia_dest_blend_factor:5; 599 unsigned int ia_src_blend_factor:5; 600 unsigned int ia_blend_function:3; 601 unsigned int stats_enable:1; 602 unsigned int logicop_func:4; 603 unsigned int pad1:10; 604 unsigned int round_disable:1; 605 unsigned int dither_enable:1; 606 } cc5; 607 608 struct { 609 unsigned int clamp_post_alpha_blend:1; 610 unsigned int clamp_pre_alpha_blend:1; 611 unsigned int clamp_range:2; 612 unsigned int pad0:11; 613 unsigned int y_dither_offset:2; 614 unsigned int x_dither_offset:2; 615 unsigned int dest_blend_factor:5; 616 unsigned int src_blend_factor:5; 617 unsigned int blend_function:3; 618 } cc6; 619 620 struct { 621 union { 622 float f; 623 unsigned char ub[4]; 624 } alpha_ref; 625 } cc7; 626 }; 627 628 #endif 629