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Searched refs:d_regs (Results 1 – 3 of 3) sorted by relevance

/external/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulationStateARM.cpp58 m_vfp_regs.d_regs[idx - 16] = value; in LoadPseudoRegistersFromFrame()
79 m_vfp_regs.d_regs[idx - 16] = value; in StorePseudoRegisterValue()
95 value = m_vfp_regs.d_regs[idx]; in ReadPseudoRegisterValue()
102 value = m_vfp_regs.d_regs[idx - 16]; in ReadPseudoRegisterValue()
117 m_vfp_regs.d_regs[i] = 0; in ClearPseudoRegisters()
268 if (m_vfp_regs.d_regs[i] != other_state.m_vfp_regs.d_regs[i]) in CompareState()
DEmulationStateARM.h68 uint64_t d_regs[16]; // dregs 16-31 member
/external/mesa3d/src/intel/compiler/
Dbrw_fs.cpp4010 unsigned int d_regs = (q_regs + 1) / 2; in lower_mul_qword_inst() local
4013 fs_reg ad(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD); in lower_mul_qword_inst()
4014 fs_reg bc(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD); in lower_mul_qword_inst()
4021 fs_reg bd_high(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD); in lower_mul_qword_inst()
4022 fs_reg bd_low(VGRF, alloc.allocate(d_regs), BRW_REGISTER_TYPE_UD); in lower_mul_qword_inst()