Searched refs:db_htile_surface (Results 1 – 8 of 8) sorted by relevance
2403 surf->db_htile_surface = 0; in si_init_depth_surface()2443 surf->db_htile_surface = in si_init_depth_surface()2446 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in si_init_depth_surface()2514 surf->db_htile_surface = S_028ABC_FULL_CACHE(1); in si_init_depth_surface()3112 unsigned db_htile_surface = zb->db_htile_surface; in si_emit_framebuffer_state() local3194 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in si_emit_framebuffer_state()3227 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, db_htile_surface); in si_emit_framebuffer_state()
431 unsigned db_htile_surface; member
282 unsigned db_htile_surface; member
1073 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) | in r600_init_depth_surface()1551 if (a->rsurf && a->rsurf->db_htile_surface) { in r600_emit_db_state()1556 radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); in r600_emit_db_state()1601 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) { in r600_emit_db_misc_state()
1432 surf->db_htile_surface = S_028ABC_HTILE_WIDTH(1) | in evergreen_init_depth_surface()2052 if (a->rsurf && a->rsurf->db_htile_surface) { in evergreen_emit_db_state()2057 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); in evergreen_emit_db_state()
7030 ds->db_htile_surface = 0; in radv_initialise_ds_surface()7080 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) | in radv_initialise_ds_surface()7084 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1); in radv_initialise_ds_surface()7148 ds->db_htile_surface = S_028ABC_FULL_CACHE(1); in radv_initialise_ds_surface()7154 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1); in radv_initialise_ds_surface()
1253 uint32_t db_htile_surface; member
1749 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface); in radv_emit_fb_ds_state()