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Searched refs:dcc_alignment (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/amd/common/
Dac_surface.h239 uint32_t dcc_alignment; member
Dac_surface.c584 surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign); in gfx6_compute_level()
1038 surf->dcc_alignment = 1; in gfx6_compute_surface()
1189 surf->dcc_size = align64(surf->surf_size >> 8, surf->dcc_alignment * 4); in gfx6_compute_surface()
1532 surf->dcc_alignment = dout.dccRamBaseAlign; in gfx9_compute_miptree()
1577 surf->u.gfx9.display_dcc_alignment = surf->dcc_alignment; in gfx9_compute_miptree()
2150 surf->dcc_offset = align64(surf->total_size, surf->dcc_alignment); in ac_compute_surface()
2152 surf->alignment = MAX2(surf->alignment, surf->dcc_alignment); in ac_compute_surface()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_texture.c878 tex->surface.dcc_offset, tex->surface.dcc_size, tex->surface.dcc_alignment, in si_print_texture_info()
923 tex->surface.dcc_offset, tex->surface.dcc_size, tex->surface.dcc_alignment); in si_print_texture_info()
2180 tex->surface.dcc_size, tex->surface.dcc_alignment); in vi_separate_dcc_try_enable()
Dsi_descriptors.c346 dcc_tile_swizzle &= tex->surface.dcc_alignment - 1; in si_set_mutable_tex_desc_fields()
Dsi_state.c2955 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8; in si_emit_framebuffer_state()
/external/mesa3d/src/amd/vulkan/
Dradv_image.c664 dcc_tile_swizzle &= plane->surface.dcc_alignment - 1; in si_set_mutable_tex_desc_fields()
Dradv_device.c6808 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8; in radv_initialise_color_surface()