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/external/mesa3d/src/util/
Ddriconf.h72 #define DRI_CONF_OPT_B(_name, def, _desc) { \ argument
78 .value = { ._bool = def }, \
81 #define DRI_CONF_OPT_I(_name, def, min, max, _desc) { \ argument
88 .value = { ._int = def }, \
91 #define DRI_CONF_OPT_F(_name, def, min, max, _desc) { \ argument
98 .value = { ._float = def }, \
101 #define DRI_CONF_OPT_E(_name, def, min, max, _desc, values) { \ argument
108 .value = { ._int = def }, \
112 #define DRI_CONF_OPT_S(_name, def, _desc) { \ argument
118 .value = { ._string = #def }, \
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
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/external/llvm/lib/Target/ARM/
DARMSchedule.td32 // def WriteALUsr : SchedWrite;
33 // def ReadAdvanceALUsr : ScheRead;
36 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
45 // def P01 : ProcResource<3>; // ALU unit (3 of it).
48 // def : WriteRes<WriteALUsr, [P01, P01]> {
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
58 def WriteALU : SchedWrite;
59 def ReadALU : SchedRead;
62 def WriteALUsi : SchedWrite; // Shift by immediate.
63 def WriteALUsr : SchedWrite; // Shift by register.
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/external/clang/include/clang/Basic/
DStmtNodes.td12 def NullStmt : Stmt;
13 def CompoundStmt : Stmt;
14 def LabelStmt : Stmt;
15 def AttributedStmt : Stmt;
16 def IfStmt : Stmt;
17 def SwitchStmt : Stmt;
18 def WhileStmt : Stmt;
19 def DoStmt : Stmt;
20 def ForStmt : Stmt;
21 def GotoStmt : Stmt;
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DDeclNodes.td13 def TranslationUnit : Decl, DeclContext;
14 def PragmaComment : Decl;
15 def PragmaDetectMismatch : Decl;
16 def ExternCContext : Decl, DeclContext;
17 def Named : Decl<1>;
18 def Namespace : DDecl<Named>, DeclContext;
19 def UsingDirective : DDecl<Named>;
20 def NamespaceAlias : DDecl<Named>;
21 def Label : DDecl<Named>;
22 def Type : DDecl<Named, 1>;
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/external/llvm-project/llvm/lib/Target/ARM/
DARMSchedule.td31 // def WriteALUsr : SchedWrite;
32 // def ReadAdvanceALUsr : ScheRead;
35 // def ADDrs : I<>, Sched<[WriteALUsr, ReadAdvanceALUsr, ReadDefault,
44 // def P01 : ProcResource<3>; // ALU unit (3 of it).
47 // def : WriteRes<WriteALUsr, [P01, P01]> {
54 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
60 def WriteALU : SchedWrite;
61 def ReadALU : SchedRead;
64 def WriteALUsi : SchedWrite; // Shift by immediate.
65 def WriteALUsr : SchedWrite; // Shift by register.
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/external/llvm/lib/Target/X86/
DX86Schedule.td17 def ReadAfterLd : SchedRead;
21 def WriteRMW : SchedWrite;
35 def Ld : SchedWrite;
37 def NAME : X86FoldableSchedWrite {
45 def WriteIMulH : SchedWrite; // Integer multiplication, high part.
47 def WriteLEA : SchedWrite; // LEA instructions can't fold loads.
53 def WriteLoad : SchedWrite;
54 def WriteStore : SchedWrite;
55 def WriteMove : SchedWrite;
59 def WriteZero : SchedWrite;
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/external/llvm-project/clang/include/clang/Basic/
DStmtNodes.td9 def Stmt : StmtNode<?, 1>;
10 def NullStmt : StmtNode<Stmt>;
11 def CompoundStmt : StmtNode<Stmt>;
12 def IfStmt : StmtNode<Stmt>;
13 def SwitchStmt : StmtNode<Stmt>;
14 def WhileStmt : StmtNode<Stmt>;
15 def DoStmt : StmtNode<Stmt>;
16 def ForStmt : StmtNode<Stmt>;
17 def GotoStmt : StmtNode<Stmt>;
18 def IndirectGotoStmt : StmtNode<Stmt>;
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsHexagon.td71 def int_hexagon_circ_ldd :
76 def int_hexagon_circ_ldw :
81 def int_hexagon_circ_ldh :
86 def int_hexagon_circ_lduh :
91 def int_hexagon_circ_ldb :
96 def int_hexagon_circ_ldub :
102 def int_hexagon_circ_std :
107 def int_hexagon_circ_stw :
112 def int_hexagon_circ_sth :
117 def int_hexagon_circ_sthhi :
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/external/llvm-project/llvm/include/llvm/IR/
DIntrinsicsHexagonDep.td1084 def int_hexagon_C2_cmpeq :
1087 def int_hexagon_C2_cmpgt :
1090 def int_hexagon_C2_cmpgtu :
1093 def int_hexagon_C2_cmpeqp :
1096 def int_hexagon_C2_cmpgtp :
1099 def int_hexagon_C2_cmpgtup :
1102 def int_hexagon_A4_rcmpeqi :
1105 def int_hexagon_A4_rcmpneqi :
1108 def int_hexagon_A4_rcmpeq :
1111 def int_hexagon_A4_rcmpneq :
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DIntrinsicsAArch64.td15 def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
16 def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>;
17 def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
18 def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>;
20 def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
21 def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>;
22 def int_aarch64_stxp : Intrinsic<[llvm_i32_ty],
24 def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty],
27 def int_aarch64_clrex : Intrinsic<[]>;
29 def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
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/external/llvm/lib/Target/PowerPC/
DPPCSchedule.td13 def IIC_IntSimple : InstrItinClass;
14 def IIC_IntGeneral : InstrItinClass;
15 def IIC_IntCompare : InstrItinClass;
16 def IIC_IntISEL : InstrItinClass;
17 def IIC_IntDivD : InstrItinClass;
18 def IIC_IntDivW : InstrItinClass;
19 def IIC_IntMFFS : InstrItinClass;
20 def IIC_IntMFVSCR : InstrItinClass;
21 def IIC_IntMTFSB0 : InstrItinClass;
22 def IIC_IntMTSRD : InstrItinClass;
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/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCSchedule.td12 def IIC_IntSimple : InstrItinClass;
13 def IIC_IntGeneral : InstrItinClass;
14 def IIC_IntCompare : InstrItinClass;
15 def IIC_IntISEL : InstrItinClass;
16 def IIC_IntDivD : InstrItinClass;
17 def IIC_IntDivW : InstrItinClass;
18 def IIC_IntMFFS : InstrItinClass;
19 def IIC_IntMFVSCR : InstrItinClass;
20 def IIC_IntMTFSB0 : InstrItinClass;
21 def IIC_IntMTSRD : InstrItinClass;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVSystemOperands.td36 def SysRegsList : GenericTable {
45 def lookupSysRegByName : SearchIndex {
57 def : SysReg<"ustatus", 0x000>;
58 def : SysReg<"uie", 0x004>;
59 def : SysReg<"utvec", 0x005>;
64 def : SysReg<"uscratch", 0x040>;
65 def : SysReg<"uepc", 0x041>;
66 def : SysReg<"ucause", 0x042>;
67 def : SysReg<"utval", 0x043>;
68 def : SysReg<"uip", 0x044>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV5.td9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsV5.td9 def : T_PR_pat <M2_vrcmpys_s1, int_hexagon_M2_vrcmpys_s1>;
10 def : T_PPR_pat<M2_vrcmpys_acc_s1, int_hexagon_M2_vrcmpys_acc_s1>;
11 def : T_PR_pat <M2_vrcmpys_s1rp, int_hexagon_M2_vrcmpys_s1rp>;
14 def : T_PP_pat<M2_vradduh, int_hexagon_M2_vradduh>;
16 def: T_RP_pat<A2_addsp, int_hexagon_A2_addsp>;
17 def: T_PP_pat<A2_addpsat, int_hexagon_A2_addpsat>;
18 def: T_PP_pat<A2_minp, int_hexagon_A2_minp>;
19 def: T_PP_pat<A2_minup, int_hexagon_A2_minup>;
20 def: T_PP_pat<A2_maxp, int_hexagon_A2_maxp>;
21 def: T_PP_pat<A2_maxup, int_hexagon_A2_maxup>;
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/external/llvm-project/clang/include/clang/AST/
DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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/external/clang/include/clang/AST/
DCommentHTMLNamedCharacterReferences.td15 def : NCR<"copy", 0x000A9>;
16 def : NCR<"COPY", 0x000A9>;
17 def : NCR<"trade", 0x02122>;
18 def : NCR<"TRADE", 0x02122>;
19 def : NCR<"reg", 0x000AE>;
20 def : NCR<"REG", 0x000AE>;
21 def : NCR<"lt", 0x0003C>;
22 def : NCR<"Lt", 0x0003C>;
23 def : NCR<"LT", 0x0003C>;
24 def : NCR<"gt", 0x0003E>;
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/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVSystemOperands.td38 def SysRegsList : GenericTable {
47 def lookupSysRegByName : SearchIndex {
52 def lookupSysRegByAltName : SearchIndex {
64 def : SysReg<"ustatus", 0x000>;
65 def : SysReg<"uie", 0x004>;
66 def : SysReg<"utvec", 0x005>;
71 def : SysReg<"uscratch", 0x040>;
72 def : SysReg<"uepc", 0x041>;
73 def : SysReg<"ucause", 0x042>;
74 def : SysReg<"utval", 0x043>;
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DRISCVSchedRocket.td14 def RocketModel : SchedMachineModel {
29 def RocketUnitALU : ProcResource<1>; // Int ALU
30 def RocketUnitIMul : ProcResource<1>; // Int Multiply
31 def RocketUnitMem : ProcResource<1>; // Load/Store
32 def RocketUnitB : ProcResource<1>; // Branch
34 def RocketUnitFPALU : ProcResource<1>; // FP ALU
38 def RocketUnitIDiv : ProcResource<1>; // Int Division
39 def RocketUnitFPDivSqrt : ProcResource<1>; // FP Divide/Sqrt
47 def : WriteRes<WriteJmp, [RocketUnitB]>;
48 def : WriteRes<WriteJal, [RocketUnitB]>;
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DRISCVSchedSiFive7.td12 def SiFive7Model : SchedMachineModel {
27 def SiFive7PipeA : ProcResource<1>;
28 def SiFive7PipeB : ProcResource<1>;
32 def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
33 def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
36 def SiFive7PipeAB : ProcResGroup<[SiFive7PipeA, SiFive7PipeB]>;
39 def : WriteRes<WriteJmp, [SiFive7PipeB]>;
40 def : WriteRes<WriteJal, [SiFive7PipeB]>;
41 def : WriteRes<WriteJalr, [SiFive7PipeB]>;
42 def : WriteRes<WriteJmpReg, [SiFive7PipeB]>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUSearchableTables.td19 def RsrcIntrinsics : GenericTable {
30 def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
50 def Gfx9BufferFormat : GcnBufferFormatTable {
54 def Gfx10PlusBufferFormat : GcnBufferFormatTable {
59 def getGfx9BufferFormatInfo : SearchIndex {
63 def getGfx10PlusBufferFormatInfo : SearchIndex {
69 def : Gfx9BufferFormat< /*FORMAT_8_UNORM*/ 0x01, 8, 1, /*NUM_FORMAT_UNORM*/ 0, /*DA…
70 def : Gfx9BufferFormat< /*FORMAT_8_SNORM*/ 0x11, 8, 1, /*NUM_FORMAT_SNORM*/ 1, /*DA…
71 def : Gfx9BufferFormat< /*FORMAT_8_USCALED*/ 0x21, 8, 1, /*NUM_FORMAT_USCALED*/ 2, /*DA…
72 def : Gfx9BufferFormat< /*FORMAT_8_SSCALED*/ 0x31, 8, 1, /*NUM_FORMAT_SSCALED*/ 3, /*DA…
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/external/llvm-project/llvm/test/CodeGen/AArch64/
Dspill-fold.mir19def dead $x0, 12, implicit-def dead $x1, 12, implicit-def dead $x2, 12, implicit-def dead $x3, 12,…
33def dead $x0, 12, implicit-def dead $x1, 12, implicit-def dead $x2, 12, implicit-def dead $x3, 12,…
47def dead $d0, 12, implicit-def dead $d1, 12, implicit-def dead $d2, 12, implicit-def dead $d3, 12,…
61def dead $x0, 12, implicit-def dead $x1, 12, implicit-def dead $x2, 12, implicit-def dead $x3, 12,…
77def dead $x0, 12, implicit-def dead $x1, 12, implicit-def dead $x2, 12, implicit-def dead $x3, 12,…
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUSearchableTables.td19 def RsrcIntrinsics : GenericTable {
30 def : RsrcIntrinsic<!cast<AMDGPURsrcIntrinsic>(intr)>;
50 def Gfx9BufferFormat : GcnBufferFormatTable {
54 def Gfx10PlusBufferFormat : GcnBufferFormatTable {
59 def getGfx9BufferFormatInfo : SearchIndex {
63 def getGfx10PlusBufferFormatInfo : SearchIndex {
69 def : Gfx9BufferFormat< /*FORMAT_8_UNORM*/ 0x01, 8, 1, /*NUM_FORMAT_UNORM*/ 0, /*DA…
70 def : Gfx9BufferFormat< /*FORMAT_8_SNORM*/ 0x11, 8, 1, /*NUM_FORMAT_SNORM*/ 1, /*DA…
71 def : Gfx9BufferFormat< /*FORMAT_8_USCALED*/ 0x21, 8, 1, /*NUM_FORMAT_USCALED*/ 2, /*DA…
72 def : Gfx9BufferFormat< /*FORMAT_8_SSCALED*/ 0x31, 8, 1, /*NUM_FORMAT_SSCALED*/ 3, /*DA…
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