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Searched refs:depth_irb (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_clear.c105 struct intel_renderbuffer *depth_irb = in brw_fast_clear_depth() local
107 struct intel_mipmap_tree *mt = depth_irb->mt; in brw_fast_clear_depth()
117 if (!intel_renderbuffer_has_hiz(depth_irb)) in brw_fast_clear_depth()
157 depth_irb->mt_level - mt->first_level) % 16) != 0) in brw_fast_clear_depth()
175 const uint32_t num_layers = depth_att->Layered ? depth_irb->layer_count : 1; in brw_fast_clear_depth()
188 if (level == depth_irb->mt_level && in brw_fast_clear_depth()
189 layer >= depth_irb->mt_layer && in brw_fast_clear_depth()
190 layer < depth_irb->mt_layer + num_layers) { in brw_fast_clear_depth()
223 intel_miptree_get_aux_state(mt, depth_irb->mt_level, in brw_fast_clear_depth()
224 depth_irb->mt_layer + a); in brw_fast_clear_depth()
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Dbrw_misc_state.c204 struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); in brw_workaround_depthstencil_alignment() local
210 if (depth_irb) in brw_workaround_depthstencil_alignment()
211 depth_mt = depth_irb->mt; in brw_workaround_depthstencil_alignment()
228 if (depth_irb && invalidate_depth && in brw_workaround_depthstencil_alignment()
232 if (depth_irb) { in brw_workaround_depthstencil_alignment()
233 if (rebase_depth_stencil(brw, depth_irb, invalidate_depth)) { in brw_workaround_depthstencil_alignment()
238 stencil_irb != depth_irb && in brw_workaround_depthstencil_alignment()
240 intel_miptree_reference(&stencil_irb->mt, depth_irb->mt); in brw_workaround_depthstencil_alignment()
246 assert(stencil_irb->mt == depth_irb->mt); in brw_workaround_depthstencil_alignment()
247 assert(stencil_irb->mt_level == depth_irb->mt_level); in brw_workaround_depthstencil_alignment()
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Dgen8_depth_state.c51 struct intel_renderbuffer *depth_irb = in pma_fix_enable() local
64 const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb); in pma_fix_enable()
85 const bool depth_test_enabled = depth_irb && ctx->Depth.Test; in pma_fix_enable()
Dbrw_draw.c631 struct intel_renderbuffer *depth_irb; in brw_predraw_resolve_framebuffer() local
634 depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); in brw_predraw_resolve_framebuffer()
635 if (depth_irb && depth_irb->mt) { in brw_predraw_resolve_framebuffer()
636 intel_miptree_prepare_depth(brw, depth_irb->mt, in brw_predraw_resolve_framebuffer()
637 depth_irb->mt_level, in brw_predraw_resolve_framebuffer()
638 depth_irb->mt_layer, in brw_predraw_resolve_framebuffer()
639 depth_irb->layer_count); in brw_predraw_resolve_framebuffer()
719 struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); in brw_postdraw_set_buffers_need_resolve() local
730 if (depth_irb) { in brw_postdraw_set_buffers_need_resolve()
733 intel_miptree_finish_depth(brw, depth_irb->mt, in brw_postdraw_set_buffers_need_resolve()
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Dbrw_wm.c400 struct intel_renderbuffer *depth_irb = in brw_wm_populate_key() local
413 if (depth_irb && ctx->Depth.Test) { in brw_wm_populate_key()
DgenX_state_upload.c1180 struct intel_renderbuffer *depth_irb = in set_depth_stencil_bits() local
1190 if (depth->Test && depth_irb) { in set_depth_stencil_bits()