Searched refs:depth_stencil_alpha_state (Results 1 – 5 of 5) sorted by relevance
113 depth_stencil_state.depthTestEnable = state->depth_stencil_alpha_state->depth_test; in zink_create_gfx_pipeline()114 depth_stencil_state.depthCompareOp = state->depth_stencil_alpha_state->depth_compare_op; in zink_create_gfx_pipeline()115 depth_stencil_state.depthBoundsTestEnable = state->depth_stencil_alpha_state->depth_bounds_test; in zink_create_gfx_pipeline()116 depth_stencil_state.minDepthBounds = state->depth_stencil_alpha_state->min_depth_bounds; in zink_create_gfx_pipeline()117 depth_stencil_state.maxDepthBounds = state->depth_stencil_alpha_state->max_depth_bounds; in zink_create_gfx_pipeline()118 depth_stencil_state.stencilTestEnable = state->depth_stencil_alpha_state->stencil_test; in zink_create_gfx_pipeline()119 depth_stencil_state.front = state->depth_stencil_alpha_state->stencil_front; in zink_create_gfx_pipeline()120 depth_stencil_state.back = state->depth_stencil_alpha_state->stencil_back; in zink_create_gfx_pipeline()121 depth_stencil_state.depthWriteEnable = state->depth_stencil_alpha_state->depth_write; in zink_create_gfx_pipeline()
52 struct zink_depth_stencil_alpha_hw_state *depth_stencil_alpha_state; member
374 if (state->depth_stencil_alpha_state != &ctx->dsa_state->hw_state) { in zink_bind_depth_stencil_alpha_state()375 state->depth_stencil_alpha_state = &ctx->dsa_state->hw_state; in zink_bind_depth_stencil_alpha_state()
466 trace_dump_arg(depth_stencil_alpha_state, state); in trace_context_create_depth_stencil_alpha_state()
407 DUMP(depth_stencil_alpha_state, &dstate->dsa->state.dsa); in dd_dump_draw_vbo()