Searched refs:display_dcc_offset (Results 1 – 8 of 8) sorted by relevance
254 uint64_t display_dcc_offset; member
2111 surf->dcc_offset = surf->display_dcc_offset = 0; in ac_compute_surface()2146 surf->display_dcc_offset = align64(surf->total_size, surf->u.gfx9.display_dcc_alignment); in ac_compute_surface()2147 surf->total_size = surf->display_dcc_offset + surf->u.gfx9.display_dcc_size; in ac_compute_surface()2162 surf->display_dcc_offset = 0; in ac_surface_zero_dcc_fields()2268 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->dcc_offset; in ac_surface_get_bo_metadata()2492 if (surf->display_dcc_offset) in ac_surface_override_offset_stride()2493 surf->display_dcc_offset += offset; in ac_surface_override_offset_stride()
631 assert(tex->surface.display_dcc_offset && tex->surface.display_dcc_offset <= UINT_MAX); in si_retile_dcc()648 img[2].u.buf.offset = tex->surface.display_dcc_offset; in si_retile_dcc()
1157 if (tex->surface.display_dcc_offset) { in si_texture_create_object()1161 si_screen_clear_buffer(sscreen, &tex->buffer.b.b, tex->surface.display_dcc_offset, in si_texture_create_object()
1224 if (tex->surface.display_dcc_offset && tex->displayable_dcc_dirty) { in si_flush_resource()
2583 if (!tex->surface.display_dcc_offset) in si_update_display_dcc_dirty()
2340 - radeonsi: remove the "display_dcc_offset == 0" assertion
3236 - radeonsi: use display_dcc_offset for setting displayable_dcc_cb_mask