| /external/llvm/test/MC/Mips/ |
| D | macro-divu.s | 6 divu $25,$11
8 # CHECK-NOTRAP: divu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1b]
12 divu $24,$12
14 # CHECK-NOTRAP: divu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1b]
18 divu $25,$0
20 # CHECK-NOTRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b]
24 divu $0,$9
25 # CHECK-NOTRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
27 divu $0,$0
28 # CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
[all …]
|
| D | macro-divu-bad.s | 11 divu $25, $11
14 divu $25, $0
17 divu $0,$0
|
| D | micromips-alu-instructions.s | 40 # CHECK-EL: divu $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xbb]
83 # CHECK-EB: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c]
124 divu $0, $9, $7
|
| /external/llvm-project/llvm/test/MC/Mips/ |
| D | macro-divu.s | 6 divu $25,$11
9 # CHECK-NOTRAP: divu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1b]
14 divu $24,$12
17 # CHECK-NOTRAP: divu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1b]
22 divu $25,$0
25 divu $0,$9
26 # CHECK-NOTRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
28 divu $0,$0
29 # CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
31 divu $4,$5,$6
[all …]
|
| D | macro-remu.s | 9 # CHECK-NOTRAP: divu $zero, $4, $5 # encoding: [0x1b,0x00,0x85,0x00]
13 # CHECK-TRAP: divu $zero, $4, $5 # encoding: [0x1b,0x00,0x85,0x00]
34 # CHECK-NOTRAP: divu $zero, $4, $1 # encoding: [0x1b,0x00,0x81,0x00]
37 # CHECK-TRAP: divu $zero, $4, $1 # encoding: [0x1b,0x00,0x81,0x00]
42 # CHECK-NOTRAP: divu $zero, $4, $1 # encoding: [0x1b,0x00,0x81,0x00]
45 # CHECK-TRAP: divu $zero, $4, $1 # encoding: [0x1b,0x00,0x81,0x00]
50 # CHECK-NOTRAP: divu $zero, $4, $1 # encoding: [0x1b,0x00,0x81,0x00]
53 # CHECK-TRAP: divu $zero, $4, $1 # encoding: [0x1b,0x00,0x81,0x00]
59 # CHECK-NOTRAP: divu $zero, $4, $1 # encoding: [0x1b,0x00,0x81,0x00]
62 # CHECK-TRAP: divu $zero, $4, $1 # encoding: [0x1b,0x00,0x81,0x00]
[all …]
|
| D | macro-divu-bad.s | 11 divu $25, 11
14 divu $25, $0
17 divu $0,$0
|
| D | micromips-alu-instructions.s | 40 # CHECK-EL: divu $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xbb]
83 # CHECK-EB: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c]
124 divu $0, $9, $7
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | udiv.ll | 40 ; NOT-R6: divu $zero, $4, $5
44 ; R6: divu $2, $4, $5
47 ; MMR3: divu $zero, $4, $5
51 ; MMR6: divu $2, $4, $5
62 ; NOT-R6: divu $zero, $4, $5
66 ; R6: divu $2, $4, $5
69 ; MMR3: divu $zero, $4, $5
73 ; MMR6: divu $2, $4, $5
84 ; NOT-R6: divu $zero, $4, $5
88 ; R6: divu $2, $4, $5
[all …]
|
| D | urem.ll | 42 ; NOT-R6: divu $zero, $[[T1]], $[[T0]]
57 ; MMR3: divu $zero, $[[T1]], $[[T0]]
80 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
88 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
101 ; MMR3: divu $zero, $[[T1]], $[[T0]]
122 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
130 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
143 ; MMR3: divu $zero, $[[T1]], $[[T0]]
162 ; NOT-R6: divu $zero, $4, $5
169 ; MMR3: divu $zero, $4, $5
|
| /external/llvm-project/llvm/test/MC/VE/ |
| D | DIV.s | 6 # CHECK-INST: divu.l %s11, %s20, %s22
8 divu.l %s11, %s20, %s22
10 # CHECK-INST: divu.w %s11, 22, %s22
12 divu.w %s11, 22, %s22
|
| /external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | udiv.ll | 75 ; GP32-NEXT: divu $zero, $4, $5
82 ; GP32R6-NEXT: divu $2, $4, $5
88 ; GP64-NEXT: divu $zero, $4, $5
95 ; GP64R6-NEXT: divu $2, $4, $5
101 ; MMR3-NEXT: divu $zero, $4, $5
108 ; MMR6-NEXT: divu $2, $4, $5
119 ; GP32-NEXT: divu $zero, $4, $5
126 ; GP32R6-NEXT: divu $2, $4, $5
132 ; GP64-NEXT: divu $zero, $4, $5
139 ; GP64R6-NEXT: divu $2, $4, $5
[all …]
|
| D | urem.ll | 77 ; GP32R0R2-NEXT: divu $zero, $2, $1
88 ; GP32R2R5-NEXT: divu $zero, $2, $1
107 ; GP64R0R1-NEXT: divu $zero, $2, $1
118 ; GP64R2R5-NEXT: divu $zero, $2, $1
137 ; MMR3-NEXT: divu $zero, $3, $2
161 ; GP32R0R2-NEXT: divu $zero, $2, $1
172 ; GP32R2R5-NEXT: divu $zero, $2, $1
191 ; GP64R0R1-NEXT: divu $zero, $2, $1
202 ; GP64R2R5-NEXT: divu $zero, $2, $1
221 ; MMR3-NEXT: divu $zero, $3, $2
[all …]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | divrem.ll | 88 ; ACC32: divu $zero, $4, $5
91 ; ACC64: divu $zero, $4, $5
94 ; GPR32: divu $2, $4, $5
97 ; GPR64: divu $2, $4, $5
114 ; ACC32: divu $zero, $4, $5
117 ; ACC64: divu $zero, $4, $5
182 ; ACC32: divu $zero, $4, $5
189 ; ACC64: divu $zero, $4, $5
196 ; GPR32-DAG: divu $2, $4, $5
204 ; GPR64-DAG: divu $2, $4, $5
[all …]
|
| D | assertzext-trunc.ll | 23 ; PRE-R6: divu $zero, $4, $5
28 ; R6: divu $2, $4, $5
|
| D | divu.ll | 12 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | divrem.ll | 88 ; ACC32: divu $zero, $4, $5
91 ; ACC64: divu $zero, $4, $5
94 ; GPR32: divu $2, $4, $5
97 ; GPR64: divu $2, $4, $5
114 ; ACC32: divu $zero, $4, $5
117 ; ACC64: divu $zero, $4, $5
182 ; ACC32: divu $zero, $4, $5
189 ; ACC64: divu $zero, $4, $5
200 ; GPR32-DAG: divu $2, $4, $5
208 ; GPR64-DAG: divu $2, $4, $5
[all …]
|
| D | assertzext-trunc.ll | 23 ; PRE-R6: divu $zero, $4, $5
28 ; R6: divu $2, $4, $5
|
| D | divu.ll | 12 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
|
| D | remu.ll | 13 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
|
| /external/llvm-project/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | div1.ll | 35 define void @divu() {
36 ; CHECK-LABEL: divu:
46 ; CHECK-DAG: divu $zero, $[[J]], $[[K]]
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | div1.ll | 35 define void @divu() {
36 ; CHECK-LABEL: divu:
46 ; CHECK-DAG: divu $zero, $[[J]], $[[K]]
|
| /external/llvm-project/llvm/test/CodeGen/VE/Scalar/ |
| D | div.ll | 54 ; CHECK-NEXT: divu.l %s0, %s0, %s1
64 ; CHECK-NEXT: divu.w %s0, %s0, %s1
90 ; CHECK-NEXT: divu.w %s0, %s0, %s1
116 ; CHECK-NEXT: divu.w %s0, %s0, %s1
178 ; CHECK-NEXT: divu.l %s0, %s0, (62)0
188 ; CHECK-NEXT: divu.w %s0, %s0, (62)0
254 ; CHECK-NEXT: divu.l %s0, 3, %s1
264 ; CHECK-NEXT: divu.w %s0, 3, %s1
|
| D | rem.ll | 58 ; CHECK-NEXT: divu.l %s2, %s0, %s1
70 ; CHECK-NEXT: divu.w %s2, %s0, %s1
100 ; CHECK-NEXT: divu.w %s2, %s0, %s1
130 ; CHECK-NEXT: divu.w %s2, %s0, %s1
198 ; CHECK-NEXT: divu.l %s1, %s0, (62)0
210 ; CHECK-NEXT: divu.w %s1, %s0, (62)0
282 ; CHECK-NEXT: divu.l %s0, 3, %s1
294 ; CHECK-NEXT: divu.w %s0, 3, %s1
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ |
| D | rem_and_div.ll | 162 ; MIPS32-NEXT: divu $zero, $2, $1
179 ; MIPS32-NEXT: divu $zero, $2, $1
194 ; MIPS32-NEXT: divu $zero, $5, $4
234 ; MIPS32-NEXT: divu $zero, $2, $1
251 ; MIPS32-NEXT: divu $zero, $2, $1
266 ; MIPS32-NEXT: divu $zero, $5, $4
|
| /external/llvm-project/llvm/test/MC/RISCV/ |
| D | rv32m-valid.s | 27 # CHECK-ASM-AND-OBJ: divu gp, a0, a1
29 divu gp, a0, a1 label
|