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Searched refs:dp4 (Results 1 – 14 of 14) sorted by relevance

/external/mesa3d/src/intel/tools/tests/gen6/
Ddp4.asm1 dp4(8) m3<1>.xF g3<4>F g1<0>F { align16 NoDDClr 1Q };
2 dp4(8) m3<1>.yF g3<4>F g1.4<0>F { align16 NoDDClr,NoDDChk 1Q };
3 dp4(8) m3<1>.wF g3<4>F g2.4<0>F { align16 NoDDChk 1Q };
4 dp4(8) g6<1>.xF g3<4>F g1<0>F { align16 1Q };
5 dp4(8) m3<1>.wF g4<4>F g2.4<0>F { align16 1Q };
6 dp4(8) g26<1>.xF g24<4>F g5<0>F { align16 NoDDClr 1Q };
7 dp4(8) g26<1>.yF g24<4>F g5.4<0>F { align16 NoDDChk 1Q };
8 dp4.sat(8) m4<1>F g2<4>.xF g2<4>F { align16 1Q };
9 dp4(8) g18<1>.xF g2.4<0>F 0x3f800000F /* 1F */ { align16 1Q };
/external/mesa3d/src/intel/tools/tests/gen5/
Ddp4.asm1 dp4(8) g6<1>.xF g3<4>F g1<0>F { align16 };
2 dp4(8) g4<1>.xF g5<4>F g1<0>F { align16 NoDDClr };
3 dp4(8) g4<1>.yF g5<4>F g1.4<0>F { align16 NoDDClr,NoDDChk };
4 dp4(8) g4<1>.wF g5<4>F g2.4<0>F { align16 NoDDChk };
5 dp4(8) m5<1>.xF g4<4>F g5<4>F { align16 };
6 dp4.sat(8) m5<1>F g3<4>.xF g3<4>F { align16 };
/external/mesa3d/src/intel/tools/tests/gen4/
Ddp4.asm1 dp4(8) g6<1>.xF g3<4>F g1<0>F { align16 };
2 dp4(8) g4<1>.xF g5<4>F g1<0>F { align16 NoDDClr };
3 dp4(8) g4<1>.yF g5<4>F g1.4<0>F { align16 NoDDClr,NoDDChk };
4 dp4(8) g4<1>.wF g5<4>F g2.4<0>F { align16 NoDDChk };
5 dp4(8) m5<1>.xF g4<4>F g5<4>F { align16 };
6 dp4.sat(8) m5<1>F g3<4>.xF g3<4>F { align16 };
/external/mesa3d/src/intel/tools/tests/gen7.5/
Ddp4.asm1 dp4(8) g115<1>.xF g3<4>F g1<0>F { align16 NoDDClr 1Q };
2 dp4(8) g115<1>.yF g3<4>F g1.4<0>F { align16 NoDDClr,NoDDChk 1Q };
3 dp4(8) g115<1>.wF g3<4>F g2.4<0>F { align16 NoDDChk 1Q };
4 dp4(8) g115<1>.wF g5<4>F g2.4<0>F { align16 1Q };
5 dp4.sat(8) g116<1>F g2<4>.xF g2<4>F { align16 1Q };
6 dp4(8) g5<1>.xF g1<4>F 0x3f800000F /* 1F */ { align16 1Q };
/external/mesa3d/src/intel/tools/tests/gen7/
Ddp4.asm1 dp4(8) g115<1>.xF g3<4>F g1<0>F { align16 NoDDClr 1Q };
2 dp4(8) g115<1>.yF g3<4>F g1.4<0>F { align16 NoDDClr,NoDDChk 1Q };
3 dp4(8) g115<1>.wF g3<4>F g2.4<0>F { align16 NoDDChk 1Q };
4 dp4(8) g115<1>.wF g5<4>F g2.4<0>F { align16 1Q };
5 dp4.sat(8) g116<1>F g2<4>.xF g2<4>F { align16 1Q };
6 dp4(8) g15<1>.xF g2<4>F 0x3f800000F /* 1F */ { align16 1Q };
/external/mesa3d/src/intel/tools/tests/gen4.5/
Ddp4.asm1 dp4(8) g6<1>.xF g3<4>F g1<0>F { align16 };
2 dp4(8) g4<1>.xF g5<4>F g1<0>F { align16 NoDDClr };
3 dp4(8) g4<1>.yF g5<4>F g1.4<0>F { align16 NoDDClr,NoDDChk };
4 dp4(8) g4<1>.wF g5<4>F g2.4<0>F { align16 NoDDChk };
5 dp4(8) m5<1>.xF g4<4>F g5<4>F { align16 };
/external/mesa3d/src/intel/compiler/
Dtest_vec4_register_coalesce.cpp184 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2)); in TEST_F() local
189 EXPECT_EQ(dp4->dst.file, MRF); in TEST_F()
190 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y); in TEST_F()
202 vec4_instruction *dp4 = v->emit(v->DP4(temp, some_src_1, some_src_2)); in TEST_F() local
215 EXPECT_EQ(dp4->dst.nr, to.nr); in TEST_F()
216 EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y); in TEST_F()
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.r600.dot4.ll8 %dp4 = call float @llvm.r600.dot4(<4 x float> %src0, <4 x float> %src1) nounwind readnone
9 store float %dp4, float addrspace(1)* %out, align 4
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.r600.dot4.ll8 %dp4 = call float @llvm.r600.dot4(<4 x float> %src0, <4 x float> %src1) nounwind readnone
9 store float %dp4, float addrspace(1)* %out, align 4
/external/mesa3d/src/intel/tools/
Di965_lex.l76 dp4 { yylval.integer = BRW_OPCODE_DP4; return DP4; }
/external/swiftshader/src/Shader/
DShaderCore.hpp285 void dp4(Vector4f &dst, const Vector4f &src0, const Vector4f &src1);
DVertexProgram.cpp190 case Shader::OPCODE_DP4: dp4(d, s0, s1); break; in program()
DPixelProgram.cpp215 case Shader::OPCODE_DP4: dp4(d, s0, s1); break; in applyShader()
DShaderCore.cpp1045 void ShaderCore::dp4(Vector4f &dst, const Vector4f &src0, const Vector4f &src1) in dp4() function in sw::ShaderCore