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Searched refs:dpp_ctrl (Results 1 – 25 of 32) sorted by relevance

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/external/mesa3d/src/amd/compiler/
Daco_print_ir.cpp598 if (dpp->dpp_ctrl <= 0xff) { in print_instr_format_specific()
600 dpp->dpp_ctrl & 0x3, (dpp->dpp_ctrl >> 2) & 0x3, in print_instr_format_specific()
601 (dpp->dpp_ctrl >> 4) & 0x3, (dpp->dpp_ctrl >> 6) & 0x3); in print_instr_format_specific()
602 } else if (dpp->dpp_ctrl >= 0x101 && dpp->dpp_ctrl <= 0x10f) { in print_instr_format_specific()
603 fprintf(output, " row_shl:%d", dpp->dpp_ctrl & 0xf); in print_instr_format_specific()
604 } else if (dpp->dpp_ctrl >= 0x111 && dpp->dpp_ctrl <= 0x11f) { in print_instr_format_specific()
605 fprintf(output, " row_shr:%d", dpp->dpp_ctrl & 0xf); in print_instr_format_specific()
606 } else if (dpp->dpp_ctrl >= 0x121 && dpp->dpp_ctrl <= 0x12f) { in print_instr_format_specific()
607 fprintf(output, " row_ror:%d", dpp->dpp_ctrl & 0xf); in print_instr_format_specific()
608 } else if (dpp->dpp_ctrl == dpp_wf_sl1) { in print_instr_format_specific()
[all …]
Daco_lower_to_hw_instr.cpp201 unsigned dpp_ctrl, unsigned row_mask, unsigned bank_mask, bool bound_ctrl, in emit_int64_dpp_op() argument
217 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
221 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
224 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
227 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
229 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
232 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
234 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
237 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
239 dpp_ctrl, row_mask, bank_mask, bound_ctrl); in emit_int64_dpp_op()
[all …]
Daco_opt_value_numbering.cpp196 aDPP->dpp_ctrl == bDPP->dpp_ctrl && in operator ()()
Daco_instruction_selection.cpp229 uint16_t dpp_ctrl = 0xffff; in emit_masked_swizzle() local
236 dpp_ctrl = dpp_quad_perm(res[0], res[1], res[2], res[3]); in emit_masked_swizzle()
238 dpp_ctrl = dpp_row_rr(8); in emit_masked_swizzle()
240 dpp_ctrl = dpp_row_mirror; in emit_masked_swizzle()
242 dpp_ctrl = dpp_row_half_mirror; in emit_masked_swizzle()
245 if (dpp_ctrl != 0xffff) in emit_masked_swizzle()
246 return bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl); in emit_masked_swizzle()
8102 uint32_t dpp_ctrl = dpp_quad_perm(lane, lane, lane, lane); in visit_intrinsic() local
8117 emit_wqm(ctx, bld.vop1_dpp(aco_opcode::v_mov_b32, bld.def(v1), src, dpp_ctrl), tmp); in visit_intrinsic()
8119 … emit_wqm(ctx, bld.ds(aco_opcode::ds_swizzle_b32, bld.def(v1), src, (1 << 15) | dpp_ctrl), tmp); in visit_intrinsic()
[all …]
/external/llvm-project/llvm/docs/AMDGPU/
DAMDGPUAsmGFX8.rst685 …id8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
688 …8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
691 …8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
696 …8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
699 …8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
702 …8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
705 …id8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
708 …id8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
711 …8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
715 …id8_vdst32_0>`, :ref:`vsrc<amdgpu_synid8_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
[all …]
DAMDGPUAsmGFX9.rst859 …id9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
862 …9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
865 …9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
870 …9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
873 …9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
876 …9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
879 …id9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
882 …id9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
885 …9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
889 …id9_vdst32_0>`, :ref:`vsrc<amdgpu_synid9_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
[all …]
DAMDGPUAsmGFX908.rst64 …dgpu_synid908_vsrc32_0>`::ref:`f16x2<amdgpu_synid908_type_dev>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
66 …dgpu_synid908_vsrc32_0>`::ref:`i16x2<amdgpu_synid908_type_dev>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
68 …dgpu_synid908_vsrc32_0>`::ref:`i8x4<amdgpu_synid908_type_dev>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
70 …dgpu_synid908_vsrc32_0>`::ref:`i4x8<amdgpu_synid908_type_dev>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
72 …8_vsrc32_0>`::ref:`m<amdgpu_synid908_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
75 …_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid908_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
DAMDGPUAsmGFX906.rst44 …_vsrc32_0>`::ref:`m<amdgpu_synid906_mod_dpp_sdwa_abs_neg>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
46 …06_vsrc32_0>`, :ref:`vsrc1<amdgpu_synid906_vsrc32_0>` :ref:`dpp_ctrl<amdgpu_synid_dpp_…
/external/llvm/lib/Target/AMDGPU/
DVIInstructions.td132 (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask,
134 (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i32imm $row_mask),
DVIInstrFormats.td192 bits<9> dpp_ctrl;
198 let Inst{48-40} = dpp_ctrl;
DSIInstrInfo.td563 def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
1242 (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1248 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1252 (ins Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1260 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1264 (ins Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl,
1367 string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
1608 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
/external/llvm-project/llvm/lib/Target/AMDGPU/
DVOP1Instructions.td314 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
841 (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask,
843 (V_MOV_B32_dpp VGPR_32:$src, VGPR_32:$src, (as_i32timm $dpp_ctrl),
849 (i32 (int_amdgcn_update_dpp i32:$old, i32:$src, timm:$dpp_ctrl,
852 (V_MOV_B32_dpp VGPR_32:$old, VGPR_32:$src, (as_i32timm $dpp_ctrl),
DVOP2Instructions.td302 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
359 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
373 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
392 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
408 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
428 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
DSIInstrInfo.td1128 def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
1740 (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1746 Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1751 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1760 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1765 Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl,
1962 string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
DGCNDPPCombine.cpp257 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); in createDPPInst()
DVOPInstructions.td586 bits<9> dpp_ctrl;
593 let Inst{48-40} = dpp_ctrl;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DVOP1Instructions.td290 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
838 (i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
840 (V_MOV_B32_dpp $src, $src, (as_i32imm $dpp_ctrl),
846 (i32 (int_amdgcn_update_dpp i32:$old, i32:$src, timm:$dpp_ctrl, timm:$row_mask,
848 (V_MOV_B32_dpp $old, $src, (as_i32imm $dpp_ctrl),
DVOP2Instructions.td293 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
348 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
362 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
381 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
397 let AsmDPP = "$vdst, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
417 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
DSIInstrInfo.td1082 def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
1748 (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1754 Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1759 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1768 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1773 Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl,
1970 string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
DGCNDPPCombine.cpp250 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); in createDPPInst()
DVOPInstructions.td576 bits<9> dpp_ctrl;
583 let Inst{48-40} = dpp_ctrl;
DSIInstructions.td1876 (i64 (int_amdgcn_mov_dpp i64:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
1878 (V_MOV_B64_DPP_PSEUDO $src, $src, (as_i32imm $dpp_ctrl),
1884 (i64 (int_amdgcn_update_dpp i64:$old, i64:$src, timm:$dpp_ctrl, timm:$row_mask,
1886 (V_MOV_B64_DPP_PSEUDO $old, $src, (as_i32imm $dpp_ctrl),
/external/mesa3d/src/amd/llvm/
Dac_llvm_build.c3400 enum dpp_ctrl enum
3416 static inline enum dpp_ctrl dpp_quad_perm(unsigned lane0, unsigned lane1, unsigned lane2, in dpp_quad_perm()
3423 static inline enum dpp_ctrl dpp_row_sl(unsigned amount) in dpp_row_sl()
3429 static inline enum dpp_ctrl dpp_row_sr(unsigned amount) in dpp_row_sr()
3436 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask, in _ac_build_dpp() argument
3447 (LLVMValueRef[]){old, src, LLVMConstInt(ctx->i32, dpp_ctrl, 0), in _ac_build_dpp()
3456 enum dpp_ctrl dpp_ctrl, unsigned row_mask, unsigned bank_mask, in ac_build_dpp() argument
3474 _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl); in ac_build_dpp()
3479 ret = _ac_build_dpp(ctx, old, src, dpp_ctrl, row_mask, bank_mask, bound_ctrl); in ac_build_dpp()
/external/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td408 // llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td1525 // llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1532 // llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1535 // v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>

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