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Searched refs:dreg (Results 1 – 22 of 22) sorted by relevance

/external/vixl/test/aarch32/
Dtest-utils-aarch32.cc145 const DRegister& dreg) { in Equal64() argument
146 return Equal64(expected, core, core->GetDRegisterBits(dreg.GetCode())); in Equal64()
236 const DRegister& dreg) { in EqualFP64() argument
238 uint64_t result = core->GetDRegisterBits(dreg.GetCode()); in EqualFP64()
Dtest-utils-aarch32.h191 const DRegister& dreg);
196 bool EqualFP32(float expected, const RegisterDump* core, const SRegister& dreg);
199 const DRegister& dreg);
/external/vixl/test/aarch64/examples/
Dtest-examples.cc349 VIXL_CHECK(regs.dreg(0) == Add3DoubleC(A, B, C)); \
375 VIXL_CHECK(regs.dreg(0) == Add4DoubleC(A, B, C, D)); \
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h157 inline double dreg(unsigned code) const { in dreg() function
Dtest-utils-aarch64.cc264 return EqualFP64(expected, core, core->dreg(fpreg.GetCode())); in EqualFP64()
/external/vixl/src/aarch32/
Dassembler-aarch32.cc4375 const DRegister& dreg = dreglist.GetFirstDRegister(); in fldmdbx() local
4377 EmitT32_32(0xed300b01U | (rn.GetCode() << 16) | dreg.Encode(22, 12) | in fldmdbx()
4388 const DRegister& dreg = dreglist.GetFirstDRegister(); in fldmdbx() local
4391 dreg.Encode(22, 12) | (len & 0xff)); in fldmdbx()
4409 const DRegister& dreg = dreglist.GetFirstDRegister(); in fldmiax() local
4412 (write_back.GetWriteBackUint32() << 21) | dreg.Encode(22, 12) | in fldmiax()
4423 const DRegister& dreg = dreglist.GetFirstDRegister(); in fldmiax() local
4426 (write_back.GetWriteBackUint32() << 21) | dreg.Encode(22, 12) | in fldmiax()
4446 const DRegister& dreg = dreglist.GetFirstDRegister(); in fstmdbx() local
4448 EmitT32_32(0xed200b01U | (rn.GetCode() << 16) | dreg.Encode(22, 12) | in fstmdbx()
[all …]
/external/llvm/test/CodeGen/ARM/
Dvector-load.ll227 ; Make sure we don't break smaller-than-dreg extloads.
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvector-load.ll227 ; Make sure we don't break smaller-than-dreg extloads.
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_from_tgsi.cpp3856 Value *dreg = getSSA(8); in handleInstruction() local
3859 mkOp2(OP_MERGE, TYPE_U64, dreg, src0, src1); in handleInstruction()
3860 Instruction *cvt = mkCvt(OP_CVT, dstTy, dst0[c], srcTy, dreg); in handleInstruction()
3887 Value *dreg = getSSA(8); in handleInstruction() local
3888 Instruction *cvt = mkCvt(OP_CVT, dstTy, dreg, srcTy, fetchSrc(0, c / 2)); in handleInstruction()
3891 mkSplit(&dst0[c], 4, dreg); in handleInstruction()
Dnv50_ir_lowering_nvc0.cpp1738 Value *dreg = bld.getSSA(typeSizeof(ty)); in handleCasExch() local
1740 bld.mkOp2(OP_MERGE, ty, dreg, cas->getSrc(1), cas->getSrc(2)); in handleCasExch()
1741 cas->setSrc(1, dreg); in handleCasExch()
1742 cas->setSrc(2, dreg); in handleCasExch()
/external/iptables/iptables/
Dnft.c1077 gen_payload(uint32_t base, uint32_t offset, uint32_t len, uint32_t dreg) in gen_payload() argument
1086 nftnl_expr_set_u32(e, NFTNL_EXPR_PAYLOAD_DREG, dreg); in gen_payload()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_shader.c1203 int dreg = d->Semantic.Name == TGSI_SEMANTIC_TESSINNER ? 3 : 2; in tgsi_declaration() local
1217 do_lds_fetch_values(ctx, temp_reg, dreg, 0xf); in tgsi_declaration()
3187 int dreg = ctx->shader->output[output_idx].gpr; in r600_tess_factor_read() local
3204 do_lds_fetch_values(ctx, temp_reg, dreg, ((1u << nc) - 1)); in r600_tess_factor_read()
/external/vixl/src/aarch64/
Dsimulator-aarch64.h1488 VIXL_DEPRECATED("ReadDRegister", double dreg(unsigned code) const) {
/external/hyphenation-patterns/de/
Dhyph-de-ch-1901.pat.txt3972 2dreg
Dhyph-de-1901.pat.txt4025 2dreg
Dhyph-de-1996.pat.txt3988 2dreg
/external/kotlinx.coroutines/benchmarks/src/jmh/resources/
Dwords.shakespeare.txt.gz1a 2A 3Aaron 4AARON 5abaissiez 6abandon 7abandoned 8abase 9Abase 10 ...
Dospd.txt.gz
/external/hyphenation-patterns/nn/
Dhyph-nn.pat.txt4902 9dreg.
/external/hyphenation-patterns/nb/
Dhyph-nb.pat.txt4902 9dreg.
/external/cldr/tools/java/org/unicode/cldr/util/data/transforms/
Dinternal_raw_IPA-old.txt57965 dreg drɛg
Dinternal_raw_IPA.txt48977 dreg %32301 drɛg