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Searched refs:dst_regs (Results 1 – 8 of 8) sorted by relevance

/external/mesa3d/src/intel/compiler/
Dbrw_eu_validate.c1456 unsigned dst_regs = registers_read(dst_access_mask); in region_alignment_rules() local
1475 if (dst_regs == 1 && (src0_regs == 2 || src1_regs == 2)) { in region_alignment_rules()
1527 if (dst_regs == 2) { in region_alignment_rules()
1574 if (devinfo->gen <= 7 && dst_regs == 2) { in region_alignment_rules()
1639 if (devinfo->gen <= 7 && dst_regs == 2) { in region_alignment_rules()
/external/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td262 bits<3> dst_regs;
269 let Inst{9-7} = dst_regs;
DMicroMipsInstrInfo.td230 MicroMipsInst16<(outs movep_regpair:$dst_regs), (ins RO:$rs, RO:$rt),
231 !strconcat(opstr, "\t$dst_regs, $rs, $rt"), [],
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td274 bits<3> dst_regs;
281 let Inst{9-7} = dst_regs;
DMicroMips32r6InstrFormats.td736 bits<3> dst_regs;
743 let Inst{9-7} = dst_regs;
/external/llvm-project/llvm/lib/Target/Mips/
DMicroMips32r6InstrFormats.td736 bits<3> dst_regs;
743 let Inst{9-7} = dst_regs;
DMicroMipsInstrFormats.td274 bits<3> dst_regs;
281 let Inst{9-7} = dst_regs;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc3158 // op: dst_regs
3175 // op: dst_regs