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Searched refs:elt0 (Results 1 – 25 of 44) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dreduce-load-width-alignment.ll22 %elt0 = extractelement <2 x i32> %vec, i32 0
23 store i32 %elt0, i32 addrspace(1)* %out
33 %elt0 = extractelement <2 x i32> %vec, i32 1
34 store i32 %elt0, i32 addrspace(1)* %out
Dsign_extend.ll86 %elt0 = extractelement <4 x i32> %ext, i32 0
90 store volatile i32 %elt0, i32 addrspace(1)* %out
112 %elt0 = extractelement <4 x i32> %ext, i32 0
116 store volatile i32 %elt0, i32 addrspace(1)* %out
133 %elt0 = extractelement <4 x i32> %ext, i32 0
137 store volatile i32 %elt0, i32 addrspace(1)* %out
156 %elt0 = extractelement <4 x i32> %ext, i32 0
160 store volatile i32 %elt0, i32 addrspace(1)* %out
Dextract-vector-elt-build-vector-combine.ll20 %elt0 = load volatile i32, i32 addrspace(1)* %in
25 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
62 %elt0 = load volatile i32, i32 addrspace(1)* %in
67 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
106 %elt0 = load volatile i32, i32 addrspace(1)* %in
111 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
Dextract_vector_elt-i64.ll13 %elt0 = extractelement <2 x i32> %vec, i32 0
16 store volatile i32 %elt0, i32 addrspace(1)* %out
Dextractelt-to-trunc.ll51 %elt0 = extractelement <4 x i32> %vec, i32 0
52 store i32 %elt0, i32 addrspace(1)* %out
Dds_read2_superreg.ll50 %elt0 = extractelement <4 x float> %val0, i32 0
55 %add0 = fadd float %elt0, %elt2
75 %elt0 = extractelement <3 x float> %val0, i32 0
79 %add0 = fadd float %elt0, %elt2
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dreduce-load-width-alignment.ll22 %elt0 = extractelement <2 x i32> %vec, i32 0
23 store i32 %elt0, i32 addrspace(1)* %out
33 %elt0 = extractelement <2 x i32> %vec, i32 1
34 store i32 %elt0, i32 addrspace(1)* %out
Dextract-vector-elt-build-vector-combine.ll20 %elt0 = load volatile i32, i32 addrspace(1)* %in
25 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
62 %elt0 = load volatile i32, i32 addrspace(1)* %in
67 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
106 %elt0 = load volatile i32, i32 addrspace(1)* %in
111 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
Dfneg.f16.ll141 %elt0 = extractelement <2 x half> %fneg, i32 0
144 %fmul0 = fmul half %elt0, 4.0
159 %elt0 = extractelement <2 x half> %fneg, i32 0
161 store volatile half %elt0, half addrspace(1)* undef
Dextract_vector_elt-i8.ll206 %elt0 = extractelement <8 x i8> %load, i32 0
210 store volatile i8 %elt0, i8 addrspace(1)* undef, align 1
225 %elt0 = extractelement <8 x i8> %load, i32 0
229 store volatile i8 %elt0, i8 addrspace(1)* undef, align 1
260 %elt0 = extractelement <16 x i8> %load, i32 0
264 store volatile i8 %elt0, i8 addrspace(1)* undef, align 1
Dfabs.f16.ll169 %elt0 = extractelement <2 x half> %fabs, i32 0
172 %fmul0 = fmul half %elt0, 4.0
193 %elt0 = extractelement <2 x half> %fabs, i32 0
195 store volatile half %elt0, half addrspace(1)* undef
Dextract_vector_elt-i64.ll13 %elt0 = extractelement <2 x i32> %vec, i32 0
16 store volatile i32 %elt0, i32 addrspace(1)* %out
Dds_read2_superreg.ll50 %elt0 = extractelement <4 x float> %val0, i32 0
55 %add0 = fadd float %elt0, %elt2
75 %elt0 = extractelement <3 x float> %val0, i32 0
79 %add0 = fadd float %elt0, %elt2
Dsign_extend.ll387 %elt0 = extractelement <4 x i32> %ext, i32 0
391 store volatile i32 %elt0, i32 addrspace(1)* %out
452 %elt0 = extractelement <4 x i32> %ext, i32 0
456 store volatile i32 %elt0, i32 addrspace(1)* %out
513 %elt0 = extractelement <4 x i32> %ext, i32 0
517 store volatile i32 %elt0, i32 addrspace(1)* %out
575 %elt0 = extractelement <4 x i32> %ext, i32 0
579 store volatile i32 %elt0, i32 addrspace(1)* %out
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dirtranslator-max-address-space.ll14 ; CHECK: %1(p16777215) :: (store 4 into %ir.elt0, addrspace 16777215)
16 %elt0 = extractelement <2 x i32 addrspace(16777215)*> %vptr, i32 0
17 store i32 0, i32 addrspace(16777215)* %elt0
/external/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/
Damdgcn-demanded-vector-elts.ll44 %elt0 = extractelement <2 x float> %data, i32 0
45 ret float %elt0
63 %elt0 = extractelement <4 x float> %data, i32 0
64 ret float %elt0
157 ; CHECK-NEXT: %elt0 = extractelement <2 x float> %data, i32 0
159 ; CHECK-NEXT: %ins0 = insertvalue { float, float } undef, float %elt0, 0
164 %elt0 = extractelement <4 x float> %data, i32 0
166 %ins0 = insertvalue { float, float } undef, float %elt0, 0
173 ; CHECK-NEXT: %elt0 = extractelement <3 x float> %data, i32 0
176 ; CHECK-NEXT: %ins0 = insertvalue { float, float, float } undef, float %elt0, 0
[all …]
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/AMDGPU/
Dreduction.ll27 %elt0 = extractelement <4 x half> %a, i64 0
32 %add1 = fadd fast half %elt1, %elt0
71 %elt0 = extractelement <8 x half> %vec8, i64 0
80 %add1 = fadd fast half %elt1, %elt0
141 %elt0 = extractelement <16 x half> %vec16, i64 0
158 %add1 = fadd fast half %elt1, %elt0
191 %elt0 = extractelement <4 x half> %a, i64 0
196 %add1 = fsub fast half %elt1, %elt0
225 %elt0 = extractelement <4 x i16> %a, i64 0
230 %add1 = add i16 %elt1, %elt0
[all …]
/external/llvm-project/llvm/test/CodeGen/SPARC/
Dvector-extract-elt.ll14 %elt0 = extractelement <4 x i32> %vec4, i32 0
16 %sum = add i32 %elt0, %elt1
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-shift-07.ll147 %elt0 = extractelement <16 x i8> %val, i32 7
149 %ext0 = sext i8 %elt0 to i64
161 %elt0 = extractelement <16 x i16> %val, i32 3
163 %ext0 = sext i16 %elt0 to i64
175 %elt0 = extractelement <16 x i32> %val, i32 1
177 %ext0 = sext i32 %elt0 to i64
Dvec-perm-12.ll33 %elt0 = extractelement <4 x i32> %x, i32 3
37 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
/external/llvm/test/CodeGen/SystemZ/
Dvec-shift-07.ll147 %elt0 = extractelement <16 x i8> %val, i32 7
149 %ext0 = sext i8 %elt0 to i64
161 %elt0 = extractelement <16 x i16> %val, i32 3
163 %ext0 = sext i16 %elt0 to i64
175 %elt0 = extractelement <16 x i32> %val, i32 1
177 %ext0 = sext i32 %elt0 to i64
Dvec-perm-12.ll33 %elt0 = extractelement <4 x i32> %x, i32 3
37 %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
/external/llvm-project/llvm/test/Analysis/ValueTracking/
Dsignbits-extract-elt.ll25 %elt0 = extractelement <2 x i32> %vec, i32 0
26 %ashr = ashr i32 %elt0, 5
/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/collator/
DCollationRegressionTest.java953 int elt0 = CollationElementIterator.primaryOrder(iter.next()); in Test4179216() local
959 if (elt4 != elt0 || elt5 != elt0) { in Test4179216()
962 elt0, elt4, elt5)); in Test4179216()
/external/icu/icu4j/main/tests/collate/src/com/ibm/icu/dev/test/collator/
DCollationRegressionTest.java950 int elt0 = CollationElementIterator.primaryOrder(iter.next()); in Test4179216() local
956 if (elt4 != elt0 || elt5 != elt0) { in Test4179216()
959 elt0, elt4, elt5)); in Test4179216()

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