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/external/clang/test/CXX/over/over.over/
Dp1.cpp3 template<typename T> T f0(T);
4 int f0(int);
8 int (*f0)(int); member
13 int (*f0a)(int) = f0; in test_init_f0()
14 int (*f0b)(int) = &f0; in test_init_f0()
15 int (*f0c)(int) = (f0); in test_init_f0()
16 float (*f0d)(float) = f0; in test_init_f0()
17 float (*f0e)(float) = &f0; in test_init_f0()
18 float (*f0f)(float) = (f0); in test_init_f0()
19 int (&f0g)(int) = f0; in test_init_f0()
[all …]
/external/llvm-project/clang/test/CXX/over/over.over/
Dp1.cpp5 template<typename T> T f0(T) NOEXCEPT;
6 int f0(int) NOEXCEPT;
10 int (*f0)(int); member
15 int (*f0a)(int) = f0; in test_init_f0()
16 int (*f0b)(int) = &f0; in test_init_f0()
17 int (*f0c)(int) = (f0); in test_init_f0()
18 float (*f0d)(float) = f0; in test_init_f0()
19 float (*f0e)(float) = &f0; in test_init_f0()
20 float (*f0f)(float) = (f0); in test_init_f0()
21 int (&f0g)(int) = f0; in test_init_f0()
[all …]
/external/llvm-project/llvm/test/MC/Sparc/
Dsparc-fp-instructions.s3 ! CHECK: fitos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0x80]
4 ! CHECK: fitod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x00]
5 ! CHECK: fitoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x80]
6 fitos %f0, %f4
7 fitod %f0, %f4
8 fitoq %f0, %f4
10 ! CHECK: fstoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x20]
11 ! CHECK: fdtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x40]
12 ! CHECK: fqtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x60]
13 fstoi %f0, %f4
[all …]
/external/llvm/test/MC/Sparc/
Dsparc-fp-instructions.s3 ! CHECK: fitos %f0, %f4 ! encoding: [0x89,0xa0,0x18,0x80]
4 ! CHECK: fitod %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x00]
5 ! CHECK: fitoq %f0, %f4 ! encoding: [0x89,0xa0,0x19,0x80]
6 fitos %f0, %f4
7 fitod %f0, %f4
8 fitoq %f0, %f4
10 ! CHECK: fstoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x20]
11 ! CHECK: fdtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x40]
12 ! CHECK: fqtoi %f0, %f4 ! encoding: [0x89,0xa0,0x1a,0x60]
13 fstoi %f0, %f4
[all …]
/external/llvm-project/llvm/test/MC/SystemZ/
Dinsn-bad-z196.s8 #CHECK: adtra %f0, %f0, %f0, -1
10 #CHECK: adtra %f0, %f0, %f0, 16
12 adtra %f0, %f0, %f0, -1
13 adtra %f0, %f0, %f0, 16
62 #CHECK: axtra %f0, %f0, %f0, -1
64 #CHECK: axtra %f0, %f0, %f0, 16
66 #CHECK: axtra %f0, %f0, %f2, 0
68 #CHECK: axtra %f0, %f2, %f0, 0
70 #CHECK: axtra %f2, %f0, %f0, 0
72 axtra %f0, %f0, %f0, -1
[all …]
Dinsn-good-z196.s5 #CHECK: adtra %f0, %f0, %f0, 0 # encoding: [0xb3,0xd2,0x00,0x00]
6 #CHECK: adtra %f0, %f0, %f0, 15 # encoding: [0xb3,0xd2,0x0f,0x00]
7 #CHECK: adtra %f0, %f0, %f15, 0 # encoding: [0xb3,0xd2,0xf0,0x00]
8 #CHECK: adtra %f0, %f15, %f0, 0 # encoding: [0xb3,0xd2,0x00,0x0f]
9 #CHECK: adtra %f15, %f0, %f0, 0 # encoding: [0xb3,0xd2,0x00,0xf0]
12 adtra %f0, %f0, %f0, 0
13 adtra %f0, %f0, %f0, 15
14 adtra %f0, %f0, %f15, 0
15 adtra %f0, %f15, %f0, 0
16 adtra %f15, %f0, %f0, 0
[all …]
/external/capstone/suite/MC/Sparc/
Dsparc-fp-instructions.s.cs2 0x89,0xa0,0x18,0x80 = fitos %f0, %f4
3 0x89,0xa0,0x19,0x00 = fitod %f0, %f4
4 0x89,0xa0,0x19,0x80 = fitoq %f0, %f4
5 0x89,0xa0,0x1a,0x20 = fstoi %f0, %f4
6 0x89,0xa0,0x1a,0x40 = fdtoi %f0, %f4
7 0x89,0xa0,0x1a,0x60 = fqtoi %f0, %f4
8 0x89,0xa0,0x19,0x20 = fstod %f0, %f4
9 0x89,0xa0,0x19,0xa0 = fstoq %f0, %f4
10 0x89,0xa0,0x18,0xc0 = fdtos %f0, %f4
11 0x89,0xa0,0x19,0xc0 = fdtoq %f0, %f4
[all …]
/external/mesa3d/src/intel/tools/tests/gen6/
Dcmp.asm1 cmp.ge.f0.0(8) g38<1>F g37<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
2 cmp.l.f0.0(8) g39<1>F g37<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
3 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1H };
4 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1H };
5 cmp.ge.f0.0(8) null<1>F g38<4>.xF g36<4>.xF { align16 1Q };
6 cmp.g.f0.0(8) null<1>UD g17<4>.xUD 0x00000000UD { align16 1Q };
7 cmp.ge.f0.0(8) null<1>UD g18<4>.xUD g17<4>.xUD { align16 1Q };
8 cmp.l.f0.0(8) null<1>F g4.4<0,1,0>F 0x0F /* 0F */ { align1 1Q };
9 cmp.l.f0.0(16) null<1>F g6.4<0,1,0>F 0x0F /* 0F */ { align1 1H };
10 cmp.z.f0.0(8) null<1>UD g9<4>.xUD 0x00000000UD { align16 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen7.5/
Dcmp.asm1 cmp.z.f0.0(8) g7<1>D g6<8,8,1>D g2.5<0,1,0>D { align1 1Q };
2 cmp.z.f0.0(16) g11<1>D g9<8,8,1>D g2.5<0,1,0>D { align1 1H };
3 cmp.ge.f0.0(8) null<1>F g45<4>.xF g43<4>.xF { align16 1Q switch };
4 cmp.g.f0.0(8) g18<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
5 cmp.nz.f0.0(8) null<1>D g18<4>.xyyyD 0D { align16 1Q switch };
6 cmp.g.f0.0(8) null<1>F g14<4>F 0x3f800000F /* 1F */ { align16 1Q switch };
7 cmp.le.f0.0(8) g24<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
8 cmp.ge.f0.0(8) g15<1>D (abs)g14<4>D 1D { align16 1Q };
9 cmp.ge.f0.0(8) g16<1>F g15<4>F 0x3f800000F /* 1F */ { align16 1Q };
10 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
[all …]
/external/mesa3d/src/intel/tools/tests/gen7/
Dcmp.asm1 cmp.ge.f0.0(8) null<1>F g45<4>.xF g43<4>.xF { align16 1Q switch };
2 cmp.g.f0.0(8) g18<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
3 cmp.nz.f0.0(8) null<1>D g18<4>.xyyyD 0D { align16 1Q switch };
4 cmp.g.f0.0(8) null<1>F g14<4>F 0x3f800000F /* 1F */ { align16 1Q switch };
5 cmp.le.f0.0(8) g24<1>.xyF g13<4>.zwwwF 0x3f800000F /* 1F */ { align16 1Q };
6 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
7 cmp.z.f0.0(8) null<1>D g13<4>.xyyyD g6<0>.yzzzD { align16 1Q switch };
8 cmp.ge.f0.0(8) g33<1>F g32<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
9 cmp.l.f0.0(8) g34<1>F g32<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 1Q };
10 cmp.ge.f0.0(8) g2<1>F g23<8,8,1>F g51<0,1,0>F { align1 1Q };
[all …]
/external/llvm/test/MC/SystemZ/
Dinsn-bad-z196.s36 #CHECK: cdlfbr %f0, 0, %r0, -1
38 #CHECK: cdlfbr %f0, 0, %r0, 16
40 #CHECK: cdlfbr %f0, -1, %r0, 0
42 #CHECK: cdlfbr %f0, 16, %r0, 0
44 cdlfbr %f0, 0, %r0, -1
45 cdlfbr %f0, 0, %r0, 16
46 cdlfbr %f0, -1, %r0, 0
47 cdlfbr %f0, 16, %r0, 0
50 #CHECK: cdlgbr %f0, 0, %r0, -1
52 #CHECK: cdlgbr %f0, 0, %r0, 16
[all …]
/external/mesa3d/src/intel/tools/tests/gen5/
Dcmp.asm1 cmp.ge.f0.0(8) null<1>D g12<8,8,1>D 16D { align1 };
2 cmp.ge.f0.0(16) null<1>D g14<8,8,1>D 16D { align1 compr };
3 cmp.ge.f0.0(8) null<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 };
4 cmp.ge.f0.0(16) null<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
5 cmp.ge.f0.0(8) null<1>F g5<4>.xF 0x0F /* 0F */ { align16 };
6 cmp.l.f0.0(8) null<1>F g5<4>.wF 0x43000000F /* 128F */ { align16 };
7 cmp.le.f0.0(8) g5<1>.xF g5<4>.xF 0x0F /* 0F */ { align16 };
8 cmp.nz.f0.0(8) null<1>.zD -g5<4>.xD 0D { align16 };
9 cmp.ge.f0.0(8) g6<1>F g4<8,8,1>F 0x26901d7dF /* 1e-15F */ { align1 };
10 cmp.ge.f0.0(16) g12<1>F g8<8,8,1>F 0x26901d7dF /* 1e-15F */ { align1 compr };
[all …]
Dsel.asm1 (+f0.0) sel(8) g6<1>F g3<8,8,1>F 0x0F /* 0F */ { align1 };
2 (-f0.0) sel(8) g2<1>UD g2<8,8,1>UD 0x00000000UD { align1 };
3 (+f0.0) sel(16) g10<1>F g6<8,8,1>F 0x0F /* 0F */ { align1 compr };
4 (-f0.0) sel(16) g4<1>UD g6<8,8,1>UD 0x00000000UD { align1 compr };
5 (+f0.0) sel(8) g4<1>.yF g5<4>.xF 0x0F /* 0F */ { align16 };
6 (-f0.0.z) sel(8) g4<1>.zUD g6<4>.xUD 0x00000000UD { align16 };
7 (+f0.0) sel(8) g2<1>F (abs)g4<8,8,1>F (abs)g3<8,8,1>F { align1 };
8 (+f0.0) sel(16) g4<1>F (abs)g16<8,8,1>F (abs)g8<8,8,1>F { align1 compr };
9 (+f0.0) sel(8) g2<1>UD g5<8,8,1>UD g6<8,8,1>UD { align1 };
10 (+f0.0) sel(8) m3<1>UD g4<8,8,1>UD g2<8,8,1>UD { align1 };
[all …]
/external/mesa3d/src/intel/tools/tests/gen4/
Dcmp.asm1 cmp.l.f0.0(8) null<1>F g8<4>.wF 0x0F /* 0F */ { align16 };
2 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
3 cmp.nz.f0.0(8) null<1>D g7<4>.xyzzD 0D { align16 };
4 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
5 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
6 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
7 cmp.ge.f0.0(16) g10<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
8 cmp.z.f0.0(8) g10<1>.xD g4<0>.xD 0D { align16 };
9 cmp.l.f0.0(8) g7<1>.xF g7<4>.xF 0x3189705fF /* 4e-09F */ { align16 };
10 cmp.ge.f0.0(8) g6<1>.xF g2<0>.xF g6<4>.xF { align16 };
[all …]
/external/mesa3d/src/intel/tools/tests/gen4.5/
Dcmp.asm1 cmp.nz.f0.0(8) null<1>F g3<0>.xyzzF 0x74746e64VF /* [10F, 15F, 20F, 20F]VF */ { align16…
2 cmp.nz.f0.0(8) null<1>D g7<4>.xyzzD 0D { align16 };
3 cmp.ge.f0.0(16) g6<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
4 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F 0x3189705fF /* 4e-09F */ { align1 compr };
5 cmp.l.f0.0(16) g8<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
6 cmp.ge.f0.0(16) g10<1>F g4<8,8,1>F g6<8,8,1>F { align1 compr };
7 cmp.z.f0.0(8) g10<1>.xD g4<0>.xD 0D { align16 };
8 cmp.l.f0.0(8) g7<1>.xF g7<4>.xF 0x3189705fF /* 4e-09F */ { align16 };
9 cmp.ge.f0.0(8) g6<1>.xF g2<0>.xF g6<4>.xF { align16 };
10 cmp.z.f0.0(8) null<1>F g3<0>.zwwwF g3<0>.xyyyF { align16 };
[all …]
/external/mesa3d/src/intel/tools/tests/gen9/
Dcmp.asm1 cmp.z.f0.0(8) null<1>F g20<8,8,1>F 0xbf800000F /* -1F */ { align1 1Q };
2 cmp.nz.f0.0(8) g59<1>DF g2.1<0,1,0>DF g59<4,4,1>DF { align1 1Q };
3 cmp.nz.f0.0(8) g49<1>F g47<8,8,1>F g14.1<0,1,0>F { align1 1Q };
4 cmp.nz.f0.0(8) null<1>D g7<8,8,1>D 0D { align1 1Q };
5 cmp.z.f0.0(8) g5<1>D g4<8,8,1>D g2.5<0,1,0>D { align1 1Q };
6 cmp.z.f0.0(16) g7<1>D g5<8,8,1>D g2.5<0,1,0>D { align1 1H };
7 cmp.l.f0.0(16) g28<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H };
8 cmp.ge.f0.0(16) g30<1>F g26<8,8,1>F g24<8,8,1>F { align1 1H };
9 cmp.nz.f0.0(8) g43<1>D g42<8,8,1>D g2.1<0,1,0>D { align1 1Q };
10 cmp.z.f0.0(8) g86<1>DF (abs)g6.2<0,1,0>DF g68<4,4,1>DF { align1 1Q };
[all …]
/external/mesa3d/src/intel/tools/tests/gen8/
Dcmp.asm1 cmp.z.f0.0(8) null<1>F g20<8,8,1>F 0xbf800000F /* -1F */ { align1 1Q };
2 cmp.nz.f0.0(8) g59<1>DF g2.1<0,1,0>DF g59<4,4,1>DF { align1 1Q };
3 cmp.nz.f0.0(8) g49<1>F g47<8,8,1>F g14.1<0,1,0>F { align1 1Q };
4 cmp.nz.f0.0(8) null<1>D g7<8,8,1>D 0D { align1 1Q };
5 cmp.z.f0.0(8) g5<1>D g4<8,8,1>D g2.5<0,1,0>D { align1 1Q };
6 cmp.z.f0.0(16) g7<1>D g5<8,8,1>D g2.5<0,1,0>D { align1 1H };
7 cmp.l.f0.0(16) g35<1>F g33<8,8,1>F g31<8,8,1>F { align1 1H };
8 cmp.ge.f0.0(16) g37<1>F g33<8,8,1>F g31<8,8,1>F { align1 1H };
9 cmp.nz.f0.0(8) g43<1>D g42<8,8,1>D g2.1<0,1,0>D { align1 1Q };
10 cmp.z.f0.0(8) g32<1>DF (abs)g6.2<0,1,0>DF g68<4,4,1>DF { align1 1Q };
[all …]
/external/llvm-project/clang/test/CodeGen/
Dbitfield-2.c19 int f0 : 24; member
26 return a0->f0; in f0_load()
29 return (a0->f0 = 1); in f0_store()
32 return (a0->f0 += 1); in f0_reload()
41 res ^= g0.f0; in test_0()
43 res ^= g0.f0; in test_0()
63 signed f0 : 10; member
87 res ^= g1.f0 ^ g1.f1; in test_1()
89 res ^= g1.f0 ^ g1.f1; in test_1()
108 unsigned long long f0 : 3; member
[all …]
/external/clang/test/CodeGen/
Dbitfield-2.c19 int f0 : 24; member
26 return a0->f0; in f0_load()
29 return (a0->f0 = 1); in f0_store()
32 return (a0->f0 += 1); in f0_reload()
41 res ^= g0.f0; in test_0()
43 res ^= g0.f0; in test_0()
63 signed f0 : 10; member
87 res ^= g1.f0 ^ g1.f1; in test_1()
89 res ^= g1.f0 ^ g1.f1; in test_1()
108 unsigned long long f0 : 3; member
[all …]
/external/capstone/suite/MC/SystemZ/
Dinsn-good.s.cs9 0xed,0x00,0x00,0x00,0x00,0x1a = adb %f0, 0
10 0xed,0x00,0x0f,0xff,0x00,0x1a = adb %f0, 4095
11 0xed,0x00,0x10,0x00,0x00,0x1a = adb %f0, 0(%r1)
12 0xed,0x00,0xf0,0x00,0x00,0x1a = adb %f0, 0(%r15)
13 0xed,0x01,0xff,0xff,0x00,0x1a = adb %f0, 4095(%r1, %r15)
14 0xed,0x0f,0x1f,0xff,0x00,0x1a = adb %f0, 4095(%r15, %r1)
16 0xb3,0x1a,0x00,0x00 = adbr %f0, %f0
17 0xb3,0x1a,0x00,0x0f = adbr %f0, %f15
19 0xb3,0x1a,0x00,0xf0 = adbr %f15, %f0
20 0xed,0x00,0x00,0x00,0x00,0x0a = aeb %f0, 0
[all …]
/external/llvm/test/MC/Disassembler/Sparc/
Dsparc-fp.txt4 # CHECK: fitos %f0, %f4
7 # CHECK: fitod %f0, %f4
10 # CHECK: fitoq %f0, %f4
13 # CHECK: fstoi %f0, %f4
16 # CHECK: fdtoi %f0, %f4
19 # CHECK: fqtoi %f0, %f4
22 # CHECK: fstod %f0, %f4
24 # CHECK: fstoq %f0, %f4
27 # CHECK: fdtos %f0, %f4
30 # CHECK: fdtoq %f0, %f4
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/Sparc/
Dsparc-fp.txt4 # CHECK: fitos %f0, %f4
7 # CHECK: fitod %f0, %f4
10 # CHECK: fitoq %f0, %f4
13 # CHECK: fstoi %f0, %f4
16 # CHECK: fdtoi %f0, %f4
19 # CHECK: fqtoi %f0, %f4
22 # CHECK: fstod %f0, %f4
24 # CHECK: fstoq %f0, %f4
27 # CHECK: fdtos %f0, %f4
30 # CHECK: fdtoq %f0, %f4
[all …]
/external/llvm-project/llvm/test/MC/Mips/mips32r2/
Dvalid-fp64.s4 abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
6 abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
8 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
10 cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
12 cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
14 cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
16 cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
18 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
20 mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00]
22 mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
[all …]
/external/llvm-project/llvm/test/MC/Mips/mips32r5/
Dvalid-fp64.s4 abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
6 abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
8 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
10 cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
12 cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
14 cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
16 cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
18 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
20 mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00]
22 mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
[all …]
/external/llvm-project/llvm/test/MC/Mips/mips32r3/
Dvalid-fp64.s4 abs.d $f0, $f12 # CHECK: abs.d $f0, $f12 # encoding: [0x46,0x20,0x60,0x05]
6 abs.s $f0, $f12 # CHECK: abs.s $f0, $f12 # encoding: [0x46,0x00,0x60,0x05]
8 add.d $f0, $f2, $f4 # CHECK: add.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x00]
10 cvt.d.s $f0, $f2 # CHECK: cvt.d.s $f0, $f2 # encoding: [0x46,0x00,0x10,0x21]
12 cvt.d.w $f0, $f2 # CHECK: cvt.d.w $f0, $f2 # encoding: [0x46,0x80,0x10,0x21]
14 cvt.s.d $f0, $f2 # CHECK: cvt.s.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x20]
16 cvt.w.d $f0, $f2 # CHECK: cvt.w.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x24]
18 div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x46,0x24,0x10,0x03]
20 mfhc1 $4, $f0 # CHECK: mfhc1 $4, $f0 # encoding: [0x44,0x64,0x00,0x00]
22 mov.d $f0, $f2 # CHECK: mov.d $f0, $f2 # encoding: [0x46,0x20,0x10,0x06]
[all …]

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