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/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-flt.ll81 ; M2: mov.s $f12, $f14
82 ; M3: mov.s $f12, $f13
85 ; M2-M3: mov.s $f0, $f12
88 ; CMOV-32: movn.s $f14, $f12, $[[T0]]
92 ; SEL-32: sel.s $f0, $f14, $f12
95 ; CMOV-64: movn.s $f13, $f12, $[[T0]]
99 ; SEL-64: sel.s $f0, $f13, $f12
102 ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]]
113 ; M2: c.olt.s $f12, $f14
114 ; M3: c.olt.s $f12, $f13
[all …]
Dselect-dbl.ll94 ; M2: mov.d $f12, $f14
97 ; M2: mov.d $f0, $f12
101 ; CMOV-32: movn.d $f14, $f12, $[[T1]]
106 ; SEL-32: sel.d $f0, $f14, $f12
111 ; M3: mov.d $f12, $f13
114 ; M3: mov.d $f0, $f12
117 ; CMOV-64: movn.d $f13, $f12, $[[T0]]
121 ; SEL-64: sel.d $f0, $f13, $f12
125 ; MM32R3: movn.d $f14, $f12, $[[T1]]
136 ; M2: c.olt.d $f12, $f14
[all …]
/external/llvm/test/MC/Mips/
Dmips-fpu-instructions.s9 # CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46]
11 # CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46]
13 # CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46]
15 # CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46]
17 # CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46]
19 # CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46]
21 # CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46]
23 # CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46]
25 # CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46]
27 # CHECK: trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46]
[all …]
/external/llvm-project/llvm/test/MC/Mips/
Dmips-fpu-instructions.s9 # CHECK: abs.d $f12, $f14 # encoding: [0x05,0x73,0x20,0x46]
11 # CHECK: add.d $f8, $f12, $f14 # encoding: [0x00,0x62,0x2e,0x46]
13 # CHECK: floor.w.d $f12, $f14 # encoding: [0x0f,0x73,0x20,0x46]
15 # CHECK: ceil.w.d $f12, $f14 # encoding: [0x0e,0x73,0x20,0x46]
17 # CHECK: mul.d $f8, $f12, $f14 # encoding: [0x02,0x62,0x2e,0x46]
19 # CHECK: neg.d $f12, $f14 # encoding: [0x07,0x73,0x20,0x46]
21 # CHECK: round.w.d $f12, $f14 # encoding: [0x0c,0x73,0x20,0x46]
23 # CHECK: sqrt.d $f12, $f14 # encoding: [0x04,0x73,0x20,0x46]
25 # CHECK: sub.d $f8, $f12, $f14 # encoding: [0x01,0x62,0x2e,0x46]
27 # CHECK: trunc.w.d $f12, $f14 # encoding: [0x0d,0x73,0x20,0x46]
[all …]
/external/capstone/suite/MC/Mips/
Dmips-fpu-instructions.s.cs2 0x05,0x73,0x20,0x46 = abs.d $f12, $f14
4 0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14
6 0x0f,0x73,0x20,0x46 = floor.w.d $f12, $f14
8 0x0e,0x73,0x20,0x46 = ceil.w.d $f12, $f14
10 0x02,0x62,0x2e,0x46 = mul.d $f8, $f12, $f14
12 0x07,0x73,0x20,0x46 = neg.d $f12, $f14
14 0x0c,0x73,0x20,0x46 = round.w.d $f12, $f14
16 0x04,0x73,0x20,0x46 = sqrt.d $f12, $f14
18 0x01,0x62,0x2e,0x46 = sub.d $f8, $f12, $f14
20 0x0d,0x73,0x20,0x46 = trunc.w.d $f12, $f14
[all …]
/external/llvm/test/CodeGen/Mips/
Dfcmp.ll43 ; 32-C-DAG: c.eq.s $f12, $f14
47 ; 64-C-DAG: c.eq.s $f12, $f13
50 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
54 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
60 ; MM32R3-DAG: c.eq.s $f12, $f14
63 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
64 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
77 ; 32-C-DAG: c.ule.s $f12, $f14
81 ; 64-C-DAG: c.ule.s $f12, $f13
84 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
[all …]
Dfmadd1.ll26 ; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
32 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
37 ; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
42 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
46 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
50 ; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
66 ; 32-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
72 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
77 ; 32R6-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
82 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
Dfpbr.ll12 ; 32-FCC: c.eq.s $f12, $f14
13 ; 64-FCC: c.eq.s $f12, $f13
16 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
47 ; 32-FCC: c.olt.s $f12, $f14
48 ; 64-FCC: c.olt.s $f12, $f13
51 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
52 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
77 ; 32-FCC: c.ole.s $f12, $f14
78 ; 64-FCC: c.ole.s $f12, $f13
[all …]
Do32_cc.ll6 ; $f12, $f14
8 ; ALL-DAG: ldc1 $f12, %lo
18 ; $f12, $f14
20 ; ALL-DAG: lwc1 $f12, %lo
30 ; $f12, $f14
32 ; ALL-DAG: lwc1 $f12, %lo
42 ; $f12, $f14
44 ; ALL-DAG: ldc1 $f12, %lo
68 ; $f12, $6, stack
70 ; ALL-DAG: ldc1 $f12, %lo
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-flt.ll119 ; M2-NEXT: mov.s $f0, $f12
131 ; CMOV32R1-NEXT: movn.s $f0, $f12, $1
138 ; CMOV32R2-NEXT: movn.s $f0, $f12, $1
144 ; 32R6-NEXT: sel.s $f0, $f14, $f12
150 ; M3-NEXT: mov.s $f0, $f12
162 ; CMOV64-NEXT: movn.s $f0, $f12, $1
168 ; 64R6-NEXT: sel.s $f0, $f13, $f12
175 ; MM32R3: movn.s $f0, $f12, $2 # <MCInst #{{.*}} MOVN_I_S_MM
180 ; MM32R6-NEXT: sel.s $f0, $f14, $f12
191 ; M2-NEXT: c.olt.s $f12, $f14
[all …]
Dselect-dbl.ll128 ; M2-NEXT: mov.d $f0, $f12
141 ; CMOV32R1-NEXT: movn.d $f0, $f12, $1
149 ; CMOV32R2-NEXT: movn.d $f0, $f12, $1
156 ; 32R6-NEXT: sel.d $f0, $f14, $f12
162 ; M3-NEXT: mov.d $f0, $f12
174 ; CMOV64-NEXT: movn.d $f0, $f12, $1
180 ; 64R6-NEXT: sel.d $f0, $f13, $f12
188 ; MM32R3: movn.d $f0, $f12, $2 # <MCInst #{{.*}} MOVN_I_D32_MM
194 ; MM32R6-NEXT: sel.d $f0, $f14, $f12
205 ; M2-NEXT: c.olt.d $f12, $f14
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/
Dfcmp.ll41 ; 32-C-DAG: c.eq.s $f12, $f14
45 ; 64-C-DAG: c.eq.s $f12, $f13
48 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
52 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
58 ; MM32R3-DAG: c.eq.s $f12, $f14
61 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
74 ; 32-C-DAG: c.ule.s $f12, $f14
78 ; 64-C-DAG: c.ule.s $f12, $f13
81 ; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
85 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
[all …]
Dfmadd1.ll37 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
43 ; 32R2: madd.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
48 ; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
53 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
57 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
61 ; 64R6-NOMADD-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
77 ; 32-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
83 ; 32R2: msub.s $[[T1:f[0-9]+]], $[[T0]], $f12, $f14
88 ; 32R6-NOMADD-DAG: mul.s $[[T1:f[0-9]+]], $f12, $f14
93 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
Do32_cc.ll6 ; $f12, $f14
8 ; ALL-DAG: ldc1 $f12, %lo
18 ; $f12, $f14
20 ; ALL-DAG: lwc1 $f12, %lo
30 ; $f12, $f14
32 ; ALL-DAG: lwc1 $f12, %lo
42 ; $f12, $f14
44 ; ALL-DAG: ldc1 $f12, %lo
68 ; $f12, $6, stack
70 ; ALL-DAG: ldc1 $f12, %lo
[all …]
Dfpbr.ll12 ; 32-FCC: c.eq.s $f12, $f14
14 ; 64-FCC: c.eq.s $f12, $f13
17 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
18 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
48 ; 32-FCC: c.olt.s $f12, $f14
50 ; 64-FCC: c.olt.s $f12, $f13
53 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
54 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
79 ; 32-FCC: c.ole.s $f12, $f14
81 ; 64-FCC: c.ole.s $f12, $f13
[all …]
Dnmadd.ll18 ; CHECK-NM-64: nmadd.s $f0, $f14, $f12, $f13
19 ; CHECK-NM: nmadd.s $f0, $f0, $f12, $f14
21 ; CHECK-NOT-NM-64: mul.s $f0, $f12, $f13
23 ; CHECK-NOT-NM: mul.s $f0, $f12, $f14
36 ; CHECK-NM-64: nmadd.d $f0, $f14, $f12, $f13
37 ; CHECK-NM: nmadd.d $f0, $f0, $f12, $f14
39 ; CHECK-NOT-NM-64: mul.d $f0, $f12, $f13
41 ; CHECK-NOT-NM: mul.d $f0, $f12, $f14
54 ; CHECK-NM-64: nmsub.s $f0, $f14, $f12, $f13
55 ; CHECK-NM: nmsub.s $f0, $f0, $f12, $f14
[all …]
/external/llvm/test/CodeGen/X86/
Dfield-extract-use-trunc.ll4 define i32 @test(i32 %f12) nounwind {
5 %tmp7.25 = lshr i32 %f12, 16
11 define i32 @test2(i32 %f12) nounwind {
12 %f11 = shl i32 %f12, 8
17 define i32 @test3(i32 %f12) nounwind {
18 %f11 = shl i32 %f12, 13
23 define i64 @test4(i64 %f12) nounwind {
24 %f11 = shl i64 %f12, 32
29 define i16 @test5(i16 %f12) nounwind {
30 %f11 = shl i16 %f12, 2
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dceil_and_floor.mir18 liveins: $f12
21 ; FP32: liveins: $f12
22 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
24 ; FP32: $f12 = COPY [[COPY]](s32)
25 ; FP32: JAL &ceilf, csr_o32, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def $f0
31 ; FP64: liveins: $f12
32 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
34 ; FP64: $f12 = COPY [[COPY]](s32)
35 …; FP64: JAL &ceilf, csr_o32_fp64, implicit-def $ra, implicit-def $sp, implicit $f12, implicit-def …
40 %0:_(s32) = COPY $f12
[all …]
Dfloat_arithmetic_operations.mir23 liveins: $f12, $f14
26 ; FP32: liveins: $f12, $f14
27 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
33 ; FP64: liveins: $f12, $f14
34 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
39 %0:_(s32) = COPY $f12
52 liveins: $f12, $f14
55 ; FP32: liveins: $f12, $f14
56 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
62 ; FP64: liveins: $f12, $f14
[all …]
Dstore_4_unaligned.mir70 liveins: $f12
73 ; MIPS32: liveins: $f12
74 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
79 ; MIPS32R6: liveins: $f12
80 ; MIPS32R6: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
84 %0:_(s32) = COPY $f12
96 liveins: $f12
99 ; MIPS32: liveins: $f12
100 ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
105 ; MIPS32R6: liveins: $f12
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfloat_arithmetic_operations.mir24 liveins: $f12, $f14
27 ; FP32: liveins: $f12, $f14
28 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
34 ; FP64: liveins: $f12, $f14
35 ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
40 %0:fprb(s32) = COPY $f12
55 liveins: $f12, $f14
58 ; FP32: liveins: $f12, $f14
59 ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
65 ; FP64: liveins: $f12, $f14
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
Dfloat_arithmetic_operations.mir24 liveins: $f12, $f14
27 ; FP32: liveins: $f12, $f14
28 ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
34 ; FP64: liveins: $f12, $f14
35 ; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
40 %0:_(s32) = COPY $f12
54 liveins: $f12, $f14
57 ; FP32: liveins: $f12, $f14
58 ; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
64 ; FP64: liveins: $f12, $f14
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dfield-extract-use-trunc.ll5 define i32 @test(i32 %f12) nounwind {
16 %tmp7.25 = lshr i32 %f12, 16
22 define i32 @test2(i32 %f12) nounwind {
33 %f11 = shl i32 %f12, 8
38 define i32 @test3(i32 %f12) nounwind {
51 %f11 = shl i32 %f12, 13
56 define i64 @test4(i64 %f12) nounwind {
68 %f11 = shl i64 %f12, 32
73 define i16 @test5(i16 %f12) nounwind {
88 %f11 = shl i16 %f12, 2
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips32r2/
Dvalid-mips32r2-el.txt5 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
8 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
26 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
28 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
30 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
32 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
34 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
36 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
38 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
40 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]
/external/llvm/test/MC/Disassembler/Mips/mips32r3/
Dvalid-mips32r3-el.txt2 0x05 0x73 0x20 0x46 # CHECK: abs.d $f12, $f14
5 0x00 0x62 0x2e 0x46 # CHECK: add.d $f8, $f12, $f14
23 0x32 0x60 0x2e 0x46 # CHECK: c.eq.d $f12, $f14
25 0x30 0x60 0x2e 0x46 # CHECK: c.f.d $f12, $f14
27 0x3e 0x60 0x2e 0x46 # CHECK: c.le.d $f12, $f14
29 0x3c 0x60 0x2e 0x46 # CHECK: c.lt.d $f12, $f14
31 0x3d 0x60 0x2e 0x46 # CHECK: c.nge.d $f12, $f14
33 0x3b 0x60 0x2e 0x46 # CHECK: c.ngl.d $f12, $f14
35 0x39 0x60 0x2e 0x46 # CHECK: c.ngle.d $f12, $f14
37 0x3f 0x60 0x2e 0x46 # CHECK: c.ngt.d $f12, $f14
[all …]

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