| /external/llvm-project/flang/tools/f18/ |
| D | CMakeLists.txt | 6 add_flang_tool(f18
8 f18.cpp
11 target_link_libraries(f18
34 target_include_directories(f18
49 COMMAND f18 -fparse-only -I${include}
52 DEPENDS f18 ${FLANG_SOURCE_DIR}/module/${filename}.f90 ${depends}
54 add_custom_command(OUTPUT ${include}/${filename}.f18.mod
57 copy ${include}/${filename}.mod ${include}/${filename}.f18.mod)
59 list(APPEND MODULE_FILES ${include}/${filename}.f18.mod)
61 install(FILES ${include}/${filename}.f18.mod DESTINATION include/flang)
[all …]
|
| D | flang.sh.in | 29 ${wd}/bin/f18 -module-suffix .f18.mod -intrinsic-module-directory @FLANG_INTRINSIC_MODULES_DIR@ $*
|
| /external/llvm-project/flang/tools/f18-parse-demo/ |
| D | CMakeLists.txt | 7 add_flang_tool(f18-parse-demo
8 f18-parse-demo.cpp
12 target_link_libraries(f18-parse-demo
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-xfail-mips64r5.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
51 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
57 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
60 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
70 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-xfail-mips64r2.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
51 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
57 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
60 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
70 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-xfail-mips64r3.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
51 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
57 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
58 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
60 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
61 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
70 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| D | valid-xfail-mips64r2.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
35 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
56 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
57 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
59 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
60 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| D | valid-xfail-mips64r3.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
35 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
56 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
57 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
59 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
60 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| D | valid-xfail-mips64r5.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
35 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x4e 0x94 0xd4 0xa1 # CHECK: madd.d $f18, $f20, $f26, $f20
56 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
57 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
59 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
60 0x4d 0x54 0x74 0xb1 # CHECK: nmadd.d $f18, $f10, $f14, $f20
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| D | valid-xfail-mips4.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
31 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
33 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18
35 0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19
|
| /external/llvm-project/clang/test/CXX/dcl/dcl.fct/ |
| D | p17.cpp | 87 void f18(auto... x) requires (sizeof...(x) == 2);
92 static_assert(is_same_v<decltype(f18('c')), void>);
94 static_assert(is_same_v<decltype(f18('c', 1)), void>);
95 static_assert(is_same_v<decltype(f18('c', 1, 2)), void>);
221 void f18(C2<char> auto... x);
223 static_assert(is_same_v<decltype(f18('a', 'b')), void>);
224 static_assert(is_same_v<decltype(f18('a', 1)), void>);
226 static_assert(is_same_v<decltype(f18(2, 'a')), void>);
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-xfail.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
33 0x4d 0x9e 0x93 0x1e # CHECK: alnv.ps $f12, $f18, $f30, $8
50 0x46 0x13 0x90 0xe6 # CHECK: cvt.ps.s $f3, $f18, $f19
53 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
60 0x46 0xdf 0x8c 0x92 # CHECK: movz.ps $f18, $f17, ra
61 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18
66 0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| D | valid-mips64-xfail.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
33 0x4d 0x9e 0x93 0x1e # CHECK: alnv.ps $f12, $f18, $f30, $8
50 0x46 0x13 0x90 0xe6 # CHECK: cvt.ps.s $f3, $f18, $f19
53 0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20
60 0x46 0xdf 0x8c 0x92 # CHECK: movz.ps $f18, $f17, ra
61 0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18
66 0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-xfail-mips32r2.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
73 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-xfail-mips32r3.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
73 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-xfail-mips32r5.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
73 0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips32r2.s | 8 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
10 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
12 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm-project/flang/ |
| D | .drone.star | 11 … "git clone --depth=1 -b f18 https://github.com/flang-compiler/f18-llvm-project.git llvm-project",
37 … "git clone --depth=1 -b f18 https://github.com/flang-compiler/f18-llvm-project.git llvm-project",
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| D | valid-xfail-mips32r2.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| D | valid-xfail-mips32r5.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
|
| /external/llvm-project/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| D | valid-xfail-mips32r3.txt | 7 0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1
14 0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23
25 0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18
36 0x46 0xc4 0x90 0x3c # CHECK: c.lt.ps $f18, $f4
50 0x46 0x00 0x6c 0x8a # CHECK: ceil.l.s $f18, $f13
52 0x46 0x14 0x90 0xa6 # CHECK: cvt.ps.s $f2, $f18, $f20
63 0x46 0xdf 0x84 0x92 # CHECK: movz.ps $f18, $f16, ra
65 0x46 0xc0 0x64 0x87 # CHECK: neg.ps $f18, $f12
|
| /external/llvm-project/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips32r2.s | 9 …madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
11 …msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
13 …nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm-project/flang/tools/ |
| D | CMakeLists.txt | 9 add_subdirectory(f18)
16 add_subdirectory(f18-parse-demo)
|
| /external/llvm-project/llvm/test/MC/Mips/mips3d/ |
| D | valid.s | 5 cvt.ps.pw $f3, $f18 # CHECK: cvt.ps.pw $f3, $f18 # encoding: [0x46,0x80,0x90,0xe6]
|
| /external/linux-kselftest/tools/testing/selftests/powerpc/include/ |
| D | fpu_asm.h | 24 stfd f18,(stack_size + STACK_FRAME_MIN_SIZE - 104)(%r1); \
44 lfd f18,(stack_size + STACK_FRAME_MIN_SIZE - 104)(%r1); \
59 lfd f18,32(r3)
|