Home
last modified time | relevance | path

Searched refs:f29 (Results 1 – 25 of 221) sorted by relevance

123456789

/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dfpu_asm.h13 stfd f29,(stack_size + STACK_FRAME_MIN_SIZE - 16)(%r1); \
33 lfd f29,(stack_size + STACK_FRAME_MIN_SIZE - 16)(%r1); \
70 lfd f29,120(r3)
/external/google-breakpad/src/common/android/include/asm-mips/
Dfpregdef.h66 #define fs4f $f29
110 #define fs5 $f29
/external/llvm/test/CodeGen/PowerPC/
Dvsx-spill.ll10 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() n…
31 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() n…
51 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0…
/external/llvm-project/llvm/test/MC/Sparc/
Dsparc-fp-instructions.s141 ! CHECK: ld [%l0], %f29 ! encoding: [0xfb,0x04,0x00,0x00]
143 ld [%l0], %f29
146 ! CHECK: st %f29, [%l0] ! encoding: [0xfb,0x24,0x00,0x00]
148 st %f29, [%l0]
/external/llvm/test/MC/Sparc/
Dsparc-fp-instructions.s141 ! CHECK: ld [%l0], %f29 ! encoding: [0xfb,0x04,0x00,0x00]
143 ld [%l0], %f29
146 ! CHECK: st %f29, [%l0] ! encoding: [0xfb,0x24,0x00,0x00]
148 st %f29, [%l0]
/external/swiftshader/third_party/marl/src/
Dosfiber_asm_mips64.h68 uintptr_t f29; member
110 static_assert(offsetof(marl_fiber_context, f29) == MARL_REG_f29,
Dosfiber_asm_mips64.S45 s.d $f29, MARL_REG_f29($a0)
71 l.d $f29, MARL_REG_f29($v0)
/external/llvm/test/MC/Mips/mips3/
Dinvalid-mips5-wrong-error.s24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips4/
Dinvalid-mips5-wrong-error.s24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips2/
Dinvalid-mips5-wrong-error.s24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips5-wrong-error.s24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
Dvalid.s9 add.d $f1,$f7,$f29
27 c.ngl.d $f29,$f29
40 div.d $f29,$f20,$f27
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips5-wrong-error.s27 … c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
39 … msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
45 … plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
57 cvt.l.s $f11,$f29
66 div.d $f29,$f20,$f27
128 movz.d $f12,$f29,$9
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
57 cvt.l.s $f11,$f29
66 div.d $f29,$f20,$f27
127 movz.d $f12,$f29,$9
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
57 cvt.l.s $f11,$f29
66 div.d $f29,$f20,$f27
127 movz.d $f12,$f29,$9
/external/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll26 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
60 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
90 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
118 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
/external/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-float.ll28 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
70 ; O32-INV-NOT: sdc1 $f29,
89 ; N32-INV-NOT: sdc1 $f29,
102 ; N64-DAG: sdc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp)
/external/llvm-project/llvm/test/CodeGen/Mips/cconv/
Dcallee-saved-float.ll28 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
70 ; O32-INV-NOT: sdc1 $f29,
89 ; N32-INV-NOT: sdc1 $f29,
102 ; N64-DAG: sdc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp)
/external/llvm-project/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll26 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
60 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
90 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
118 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
/external/llvm/test/MC/Mips/mips32/
Dvalid.s11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
62 div.d $f29,$f20,$f27
112 movz.d $f12,$f29,$9
/external/llvm/test/MC/ARM/
Dsymbol-variants.s95 ldr r3, =f29(GOT_PREL)
97 @ CHECK: 78 R_ARM_GOT_PREL f29
/external/llvm-project/llvm/test/MC/ARM/
Dsymbol-variants.s95 .word f29(tlsldm)
97 @CHECK: 74 R_ARM_TLS_LDM32 f29
/external/llvm-project/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips1.s11 …c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips1.s11 …c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…

123456789