f32x4 (reference) in projects: external

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Searched refs:f32x4 (Results 1 – 25 of 27) sorted by relevance

/external/llvm-project/llvm/test/MC/WebAssembly/
D	simd-encodings.s	`91 # CHECK: f32x4.splat # encoding: [0xfd,0x13] 92 f32x4.splat 127 # CHECK: f32x4.extract_lane 3 # encoding: [0xfd,0x1f,0x03] 128 f32x4.extract_lane 3 130 # CHECK: f32x4.replace_lane 3 # encoding: [0xfd,0x20,0x03] 131 f32x4.replace_lane 3 229 # CHECK: f32x4.eq # encoding: [0xfd,0x41] 230 f32x4.eq 232 # CHECK: f32x4.ne # encoding: [0xfd,0x42] 233 f32x4.ne [all …]`
/external/llvm-project/clang/test/CodeGen/
D	builtins-wasm.c	14 typedef float f32x4 __attribute((vector_size(16))); 237 float extract_lane_f32x4(f32x4 v) { in extract_lane_f32x4() 275 f32x4 replace_lane_f32x4(f32x4 v, float x) { in replace_lane_f32x4() 737 f32x4 abs_f32x4(f32x4 x) { in abs_f32x4() 749 f32x4 min_f32x4(f32x4 x, f32x4 y) { in min_f32x4() 756 f32x4 max_f32x4(f32x4 x, f32x4 y) { in max_f32x4() 763 f32x4 pmin_f32x4(f32x4 x, f32x4 y) { in pmin_f32x4() 770 f32x4 pmax_f32x4(f32x4 x, f32x4 y) { in pmax_f32x4() 805 f32x4 ceil_f32x4(f32x4 x) { in ceil_f32x4() 811 f32x4 floor_f32x4(f32x4 x) { in floor_f32x4() [all …]
/external/llvm-project/llvm/test/CodeGen/WebAssembly/
D	simd-comparisons.ll	`791 ; NO-SIMD128-NOT: f32x4 793 ; SIMD128-NEXT: f32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}} 801 ; NO-SIMD128-NOT: f32x4 803 ; SIMD128-NEXT: f32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}} 811 ; NO-SIMD128-NOT: f32x4 813 ; SIMD128-NEXT: f32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}} 822 ; NO-SIMD128-NOT: f32x4 824 ; SIMD128-NEXT: f32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}} 833 ; NO-SIMD128-NOT: f32x4 835 ; SIMD128-NEXT: f32x4.gt $push[[R:[0-9]+]]=, $0, $1{{$}} [all …]`
D	simd-conversions.ll	`13 ; SIMD128-NEXT: f32x4.convert_i32x4_s $push[[R:[0-9]+]]=, $0 23 ; SIMD128-NEXT: f32x4.convert_i32x4_u $push[[R:[0-9]+]]=, $0 49 ; NO-SIMD128-NOT: f32x4 59 ; NO-SIMD128-NOT: f32x4`
D	simd-arith.ll	`1257 ; NO-SIMD128-NOT: f32x4 1259 ; SIMD128-NEXT: f32x4.neg $push[[R:[0-9]+]]=, $0{{$}} 1268 ; NO-SIMD128-NOT: f32x4 1270 ; SIMD128-NEXT: f32x4.abs $push[[R:[0-9]+]]=, $0{{$}} 1279 ; NO-SIMD128-NOT: f32x4 1282 ; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1292 ; NO-SIMD128-NOT: f32x4 1295 ; SIMD128-NEXT: f32x4.max $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} 1305 ; NO-SIMD128-NOT: f32x4 1308 ; SIMD128-NEXT: f32x4.min $push[[R:[0-9]+]]=, $0, $pop[[L0]]{{$}} [all …]`
D	simd.ll	`826 ; NO-SIMD128-NOT: f32x4 838 ; NO-SIMD128-NOT: f32x4 840 ; SIMD128-NEXT: f32x4.splat $push[[R:[0-9]+]]=, $0{{$}} 856 ; NO-SIMD128-NOT: f32x4 858 ; SIMD128-NEXT: f32x4.extract_lane $push[[R:[0-9]+]]=, $0, 3{{$}} 886 ; NO-SIMD128-NOT: f32x4 888 ; SIMD128-NEXT: f32x4.extract_lane $push[[R:[0-9]+]]=, $0, 0{{$}} 896 ; NO-SIMD128-NOT: f32x4 898 ; SIMD128-NEXT: f32x4.replace_lane $push[[R:[0-9]+]]=, $0, 2, $1{{$}} 906 ; NO-SIMD128-NOT: f32x4 [all …]`
D	simd-build-vector.ll	`125 ; UNIMP-NEXT: f32x4.replace_lane $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0 127 ; SIMD-VM: f32x4.splat 139 ; UNIMP-NEXT: f32x4.replace_lane $push[[L1:[0-9]+]]=, $pop[[L0]], 2, $0 141 ; SIMD-VM: f32x4.splat 333 ; SIMD-VM: f32x4.splat`
D	simd-shuffle-bitcast.ll	`12 ; CHECK-NEXT: f32x4.splat $push[[R:[0-9]+]]=, $0{{$}}`
D	simd-intrinsics.ll	507 ; NO-SIMD128-NOT: f32x4 518 ; NO-SIMD128-NOT: f32x4 700 ; SIMD128-NEXT: f32x4.pmin $push[[R:[0-9]+]]=, $0, $1{{$}} 710 ; SIMD128-NEXT: f32x4.pmax $push[[R:[0-9]+]]=, $0, $1{{$}} 720 ; SIMD128-NEXT: f32x4.ceil $push[[R:[0-9]+]]=, $0{{$}} 730 ; SIMD128-NEXT: f32x4.floor $push[[R:[0-9]+]]=, $0{{$}} 740 ; SIMD128-NEXT: f32x4.trunc $push[[R:[0-9]+]]=, $0{{$}} 750 ; SIMD128-NEXT: f32x4.nearest $push[[R:[0-9]+]]=, $0{{$}} 760 ; SIMD128-NEXT: f32x4.qfma $push[[R:[0-9]+]]=, $0, $1, $2{{$}} 772 ; SIMD128-NEXT: f32x4.qfms $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
D	simd-select.ll	`416 ; CHECK-NEXT: f32x4.lt`
/external/llvm-project/llvm/docs/AMDGPU/
D	AMDGPUAsmGFX908.rst	107 …f32x4<amdgpu_synid908_type_dev>`, :ref:`vasrc0<amdgpu_synid908_vasrc64_0>`::ref:`f16x4<amdgpu_syn… 111 …f32x4<amdgpu_synid908_type_dev>`, :ref:`vasrc0<amdgpu_synid908_vasrc32_0>`::ref:`f32<amdgpu_synid… 112 …f32x4<amdgpu_synid908_type_dev>`, :ref:`vasrc0<amdgpu_synid908_vasrc32_0>`::ref:`bf16x2<amdgpu_sy… 119 …f32x4<amdgpu_synid908_type_dev>`, :ref:`vasrc0<amdgpu_synid908_vasrc32_0>`::ref:`f32<amdgpu_synid… 120 …f32x4<amdgpu_synid908_type_dev>`, :ref:`vasrc0<amdgpu_synid908_vasrc32_0>`::ref:`bf16x2<amdgpu_sy… 121 …f32x4<amdgpu_synid908_type_dev>`, :ref:`vasrc0<amdgpu_synid908_vasrc64_0>`::ref:`f16x4<amdgpu_syn…
/external/rust/crates/rand/src/distributions/
D	float.rs	`159 float_impls! { f32x4, u32x4, f32, u32, 23, 127 } 215 test_f32! { f32x4_edge_cases, f32x4, f32x4::splat(0.0), f32x4::splat(EPSILON32) }`
D	utils.rs	`424 #[cfg(feature="simd_support")] simd_impl! { f32x4, f32, m32x4, u32x4 }`
D	uniform.rs	`983 uniform_float_impl! { f32x4, u32x4, f32, u32, 32 - 23 } 1406 t!(f32x4, f32, 32 - 23); in test_floats() 1467 t!(f32x4, f32); in test_float_assertions()`
/external/skia/modules/canvaskit/wasm_tools/SIMD/
D	wasm_simd_types.txt	`10 f32x4`
/external/llvm-project/llvm/lib/Target/WebAssembly/
D	WebAssemblyInstrSIMD.td	472 defm "" : Splat<v4f32, "f32x4", F32, splat4, 19>; 508 defm "" : ExtractLane<v4f32, "f32x4", F32, 31>; 554 defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 32>; 594 defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>; 1022 defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>; 1036 defm CEIL : SIMDUnary<v4f32, "f32x4", int_wasm_ceil, "ceil", 216>; 1037 defm FLOOR : SIMDUnary<v4f32, "f32x4", int_wasm_floor, "floor", 217>; 1038 defm TRUNC: SIMDUnary<v4f32, "f32x4", int_wasm_trunc, "trunc", 218>; 1039 defm NEAREST: SIMDUnary<v4f32, "f32x4", int_wasm_nearest, "nearest", 219>; 1050 defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>; [all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
D	WebAssemblyInstrSIMD.td	312 defm "" : Splat<v4f32, "f32x4", F32, splat4, 18>; 378 defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>; 427 defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 20>; 467 defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>; 773 defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>; 792 defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>; 830 defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>; 831 defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>; 917 defm "" : SIMDQFM<v4f32, "f32x4", 0x98>;
/external/neon_2_sse/
D	NEON_2_SSE.h	`15768 float32x4x2_t f32x4; in vtrnq_f32() local 15773 f32x4.val[0] = _mm_unpacklo_ps(a_sh, b_sh); //a0, b0, a2, b2 in vtrnq_f32() 15774 f32x4.val[1] = _mm_unpackhi_ps(a_sh, b_sh); //a1, b1, a3, b3 in vtrnq_f32() 15775 return f32x4; in vtrnq_f32() 15867 float32x4x2_t f32x4; in vzipq_f32() local 15868 f32x4.val[0] = _mm_unpacklo_ps ( a, b); in vzipq_f32() 15869 f32x4.val[1] = _mm_unpackhi_ps ( a, b); in vzipq_f32() 15870 return f32x4; in vzipq_f32()`
/external/llvm/test/CodeGen/X86/
D	avx512-intrinsics.ll	`4851 declare <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float>, <16 x float>, i32, <16 x float>… 4861 …%res = call <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float> %x0, <16 x float> %x1, i32 … 4862 …%res1 = call <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float> %x0, <16 x float> %x1, i32…`
D	avx512vl-intrinsics.ll	`4374 declare <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float>, <8 x float>, i32, <8 x float>… 4389 …%res = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32… 4390 …%res1 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i3… 4391 …%res2 = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i3…`
/external/llvm-project/llvm/test/CodeGen/X86/
D	avx512-intrinsics-upgrade.ll	`2863 declare <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float>, <16 x float>, i32, <16 x float>… 2871 …%res = call <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float> %x0, <16 x float> %x1, i32 … 2891 …%res = call <16 x float> @llvm.x86.avx512.mask.shuf.f32x4(<16 x float> %x0, <16 x float> %x1, i32 …`
D	avx512vl-intrinsics-upgrade.ll	`5561 declare <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float>, <8 x float>, i32, <8 x float>… 5569 …%res = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32… 5590 …%res = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32… 5611 …%res = call <8 x float> @llvm.x86.avx512.mask.shuf.f32x4.256(<8 x float> %x0, <8 x float> %x1, i32…`
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
D	Intrinsics.gen	`5216 x86_avx512_mask_shuf_f32x4, // llvm.x86.avx512.mask.shuf.f32x4 5217 x86_avx512_mask_shuf_f32x4_256, // llvm.x86.avx512.mask.shuf.f32x4.256 11274 "llvm.x86.avx512.mask.shuf.f32x4", 11275 "llvm.x86.avx512.mask.shuf.f32x4.256", 19214 1, // llvm.x86.avx512.mask.shuf.f32x4 19215 1, // llvm.x86.avx512.mask.shuf.f32x4.256`
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
D	Intrinsics.gen	`5216 x86_avx512_mask_shuf_f32x4, // llvm.x86.avx512.mask.shuf.f32x4 5217 x86_avx512_mask_shuf_f32x4_256, // llvm.x86.avx512.mask.shuf.f32x4.256 11274 "llvm.x86.avx512.mask.shuf.f32x4", 11275 "llvm.x86.avx512.mask.shuf.f32x4.256", 19214 1, // llvm.x86.avx512.mask.shuf.f32x4 19215 1, // llvm.x86.avx512.mask.shuf.f32x4.256`
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
D	Intrinsics.gen	`5216 x86_avx512_mask_shuf_f32x4, // llvm.x86.avx512.mask.shuf.f32x4 5217 x86_avx512_mask_shuf_f32x4_256, // llvm.x86.avx512.mask.shuf.f32x4.256 11274 "llvm.x86.avx512.mask.shuf.f32x4", 11275 "llvm.x86.avx512.mask.shuf.f32x4.256", 19214 1, // llvm.x86.avx512.mask.shuf.f32x4 19215 1, // llvm.x86.avx512.mask.shuf.f32x4.256`

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